Hitachi H8/3032 Series Hardware Manual page 272

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Contention between General Register Write and Compare Match: If a compare match occurs
in the T state of a general register write cycle, writing takes priority and the compare match
3
signal is inhibited. See figure 8-64.
ø
Address
Internal write signal
TCNT
GR
Compare match signal
Figure 8-64 Contention between General Register Write and Compare Match
General register write cycle
T T T
1 2 3
GR address
N
N
General register write data
257
N + 1
M
Inhibited