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TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
Overflow flag
0 [Clearing condition]
1 [Setting condition]
Note:
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7
6
IT
OVF
WT/
0
0
R/(W)
R/W
*
Timer enable
0 Timer disabled
•
TCNT is initialized to H'00 and halted
1 Timer enabled
•
TCNT is counting
•
CPU interrupt requests are enabled
Timer mode select
0 Interval timer: requests interval timer interrupts
1 Watchdog timer: generates a reset signal
Read OVF when OVF = 1, then write 0 in OVF
TCNT changes from H'FF to H'00
Only 0 can be written, to clear the flag.
*
H'A8
5
4
3
TME
—
—
CKS2
0
1
1
R/W
—
—
R/W
Clock select 2 to 0
0
1
508
WDT
2
1
0
CKS1
CKS0
0
0
0
R/W
R/W
0
0
ø/2
1
ø/32
1
0
ø/64
1
ø/128
0
0
ø/256
1
ø/512
1
0
ø/2048
1
ø/4096
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