Operation; Mode 1; Modes 2 And 3 - Hitachi H8/3032 Series Hardware Manual

13.3 Operation

13.3.1 Mode 1

When the RAME bit is set to 1 in mode 1, accesses to addresses H'FF710 to H'FFF0F of the
H8/3032, to addresses H'FFB10 to H'FFF0F of the H8/3031, and to addresses H'FFD10 to
H'FFF0F of the H8/3030 are directed to the on-chip RAM space. When the RAME bit is cleared
to 0, accesses to such addresses are directed to the off-chip address space.

13.3.2 Modes 2 and 3

When the RAME bit is set to 1 in modes 2 and 3, accesses to addresses H'F710 to H'FF0F of the
H8/3032, to addresses H'FB10 to H'FF0F of the H8/3031, and to addresses H'FD10 to H'FF0F of
the H8/3030 are directed to the on-chip RAM space. When the RAME bit is cleared to 0, read
accesses to such addresses always return H'FF and write accesses are ignored. Note that these
addresses represent the lower 16 bits of the address.
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