Hitachi H8/3032 Series Hardware Manual page 570

Reset in T
T
3
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus outputs are held during the T
the T
ø
RES
Internal
reset signal
Address bus
(mode 1)
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
I/O port
(modes 1 to 3)
Downloaded from Elcodis.com electronic components distributor
State: Figure D-3 is a timing diagram for the case in which RES goes low during the
3
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
state of an access cycle to a two-state-access area.
2
Figure D-3 Reset during Memory Access (Reset during T
state.The same timing applies when a reset occurs in
3
Access to external address
T T T
1 2 3
554
H'000000
High impedance
High impedance
State)
3