Hitachi H8/3032 Series Hardware Manual page 7

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5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 79
5.2.3 IRQ Status Register (ISR) .............................................................................. 85
5.2.4 IRQ Enable Register (IER)............................................................................. 86
5.2.5 IRQ Sense Control Register (ISCR) ............................................................... 87
5.3 Interrupt Sources............................................................................................................. 88
5.3.1 External Interrupts .......................................................................................... 88
5.3.2 Internal Interrupts ........................................................................................... 89
5.3.3 Interrupt Vector Table ..................................................................................... 89
5.4 Interrupt Operation ......................................................................................................... 92
5.4.1 Interrupt Handling Process ............................................................................. 92
5.4.2 Interrupt Sequence .......................................................................................... 97
5.4.3 Interrupt Response Time................................................................................. 98
5.5 Usage Notes .................................................................................................................... 99
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ................ 99
5.5.2 Instructions that Inhibit Interrupts .................................................................. 100
5.5.3 Interrupts during EEPMOV Instruction Execution ........................................ 100
Section 6 Bus Controller
6.1 Overview ........................................................................................................................ 101
6.1.1 Features........................................................................................................... 101
6.1.2 Block Diagram................................................................................................ 102
6.1.3 Input/Output Pins............................................................................................ 103
6.1.4 Register Configuration.................................................................................... 103
6.2 Register Descriptions...................................................................................................... 104
6.2.1 Access State Control Register (ASTCR)........................................................ 104
6.2.2 Wait Control Register (WCR)......................................................................... 105
6.2.3 Wait State Controller Enable Register (WCER)............................................. 106
6.3 Operation ........................................................................................................................ 107
6.3.1 Area Division.................................................................................................. 107
6.3.2 Bus Control Signal Timing ............................................................................. 109
6.3.3 Wait Modes ..................................................................................................... 111
6.3.4 Interconnections with Memory (Example)..................................................... 117
6.4 Usage Notes .................................................................................................................... 118
6.4.1 Register Write Timing .................................................................................... 118
Section 7 I/O Ports
....................................................................................................... 119
7.1 Overview ........................................................................................................................ 119
7.2 Port 1 ........................................................................................................................ 122
7.2.1 Overview......................................................................................................... 122
7.2.2 Register Descriptions...................................................................................... 123
7.2.3 Pin Functions in Each Mode........................................................................... 124
............................................................................................ 101