Register Descriptions; A/D Data Registers A To D (Addra To Addrd) - Hitachi H8/3032 Series Hardware Manual

Downloaded from Elcodis.com electronic components distributor

12.2 Register Descriptions

12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

Bit 15 14 13
AD8
ADDRn AD9 AD7
Initial value 0 0 0
Read/Write R R R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the
upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an
A/D data register are reserved bits that always read 0. Table 12-3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 12.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 12-3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0 Group 1
AN AN
0 4
AN AN
1 5
AN AN
2 6
AN AN
3 7
12 11 10 9 8 7
AD6 AD4 AD2
AD5 AD3 AD1
0 0 0 0 0 0
R R R R R R
A/D conversion data
10-bit data giving an
A/D conversion result
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
375
6 5 4 3 2 1
AD0
— — — — —
0 0 0
0 0 0
R R R R R R
Reserved bits
0
—
0
R