Hitachi H8/3032 Series Hardware Manual page 17

Table 1-1 Features
Feature
CPU
Memory
Interrupt
controller
Bus controller
Downloaded from Elcodis.com electronic components distributor
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)
• Advanced mode (1-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
H8/3032
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3031
• ROM: 32 kbytes
• RAM: 1 kbyte
H8/3030
• ROM: 16 kbytes
• RAM: 512 bytes
• Six external interrupt pins: NMI, IRQ
• 21 internal interrupts
• Three selectable interrupt priority levels
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
2
to IRQ
0 4