Hitachi H8/3032 Series Hardware Manual page 279

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ITU Operating Modes
Table 8-11 (a) ITU Operating Modes (Channel 0)
TSNC TMDR
Synchro-
Operating Mode nization MDF FDIR PWM
Synchronous preset SYNC0 = 1 — —
PWM mode — —
o
Output compare A — —
o
Output compare B — —
o
Input capture A — —
o
Input capture B — —
o
Counter By compare — —
o
clearing match/input
capture A
By compare — —
o
match/input
capture B
Syn- SYNC0 = 1 — —
chronous
clear
Legend: Setting available (valid). — Setting does not affect this mode.
o
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Register Settings
TFCR TOCR
Reset-
Comple- Synchro-
mentary nized Buffer-
PWM PWM ing XTGD Select
— — — —
o
PWM0 = 1 — — — —
PWM0 = 0 — — — —
— — — —
o
PWM0 = 0 — — — —
PWM0 = 0 — — — —
— — — —
o
— — — —
o
— — — —
o
264
TOER TIOR0
Output
Level Master Clear
Enable IOA IOB Select
— —
o o o
— — —* *
o o
— — IOA2 = 0
o o
Other bits
unrestricted
— — IOB2 = 0
o o
Other bits
unrestricted
— — IOA2 = 1
o o
Other bits
unrestricted
— — IOB2 = 1
o o
Other bits
unrestricted
— — CCLR1 = 0
o o
CCLR0 = 1
— — CCLR1 = 1
o o
CCLR0 = 0
— — CCLR1 = 1
o o
CCLR0 = 1
TCR0
Clock
Select
o
o
o
o
o
o
o
o
o