Hitachi H8/3032 Series Hardware Manual page 524

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TCNT—Timer Counter
Bit 7
Initial value 0
Read/Write R/W R/W
RSTCSR—Reset Control/Status Register
Bit 7
WRST RSTOE
Initial value 0
Read/Write R/(W) * R/W
Reset output enable
0 Reset signal is not output externally
1 Reset signal is output externally
Watchdog timer reset
0 [Clearing condition]
Reset signal input at
1 [Setting condition]
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
6 5 4 3
0 0 0 0
R/W R/W R/W
Count value
6 5 4 3
— — —
0 1 1 1
— — —
RES
pin, or 0 written by software
509
H'A9 (read), WDT
H'A8 (write)
2 1 0
0 0 0
R/W R/W R/W
H'AB (read), WDT
H'AA (write)
2 1 0
— — —
1 1 1
— — —