Hitachi H8/3032 Series Hardware Manual page 6

2.9
Section 3
3.1
3.2
3.3
3.4
3.5
3.6
Section 4
4.1
4.2
4.3
4.4
4.5
4.6
Section 5
5.1
5.2
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Basic Operational Timing ............................................................................................... 51
2.9.1 Overview......................................................................................................... 51
2.9.2 On-Chip Memory Access Timing................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing ................................................. 53
2.9.4 Access to External Address Space.................................................................. 54
MCU Operating Modes
Overview ........................................................................................................................ 55
3.1.1 Operating Mode Selection .............................................................................. 55
3.1.2 Register Configuration.................................................................................... 56
Mode Control Register (MDCR) .................................................................................... 57
System Control Register (SYSCR)................................................................................. 58
Operating Mode Descriptions......................................................................................... 60
3.4.1 Mode 1 ............................................................................................................ 60
3.4.2 Mode 2 ............................................................................................................ 60
3.4.3 Mode 3 ............................................................................................................ 60
Pin Functions in Each Operating Mode.......................................................................... 61
Memory Map in Each Operating Mode.......................................................................... 61
Exception Handling
Overview ........................................................................................................................ 65
4.1.1 Exception Handling Types and Priority.......................................................... 65
4.1.2 Exception Handling Operation ....................................................................... 65
4.1.3 Exception Vector Table................................................................................... 66
Reset ........................................................................................................................ 67
4.2.1 Overview......................................................................................................... 67
4.2.2 Reset Sequence ............................................................................................... 67
4.2.3 Interrupts after Reset....................................................................................... 69
Interrupts ........................................................................................................................ 70
Trap Instruction............................................................................................................... 71
Stack Status after Exception Handling ........................................................................... 72
Notes on Stack Usage ..................................................................................................... 73
Interrupt Controller
Overview ........................................................................................................................ 75
5.1.1 Features........................................................................................................... 75
5.1.2 Block Diagram................................................................................................ 76
5.1.3 Pin Configuration............................................................................................ 77
5.1.4 Register Configuration.................................................................................... 77
Register Descriptions...................................................................................................... 78
5.2.1 System Control Register (SYSCR)................................................................. 78
........................................................................... 55
.................................................................................. 65
................................................................................... 75