Hitachi H8/3032 Series Hardware Manual page 493

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(Continued from preceding page)
Address Register
(low)
H'A0
H'A1
H'A2
H'A3
H'A4
H'A5
H'A6
H'A7
H'A8
H'A9
H'AA
H'AB
H'AC
H'AD
H'AE
H'AF
H'B0
H'B1
H'B2
H'B3
H'B4
H'B5
H'B6
H'B7
Notes: 1. The address depends on the output trigger setting.
Legend
TPC: Programmable timing pattern controller
WDT: Watchdog timer
SCI:
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Data
Bus
Name
Width
Bit 7
Bit 6
TPMR
8
TPCR
8
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
NDERB
8
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
NDERA
8
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
*1
NDRB
8
NDR15 NDR14 NDR13 NDR12 NDR11
8
NDR15 NDR14 NDR13 NDR12 —
*1
NDRA
8
NDR7
NDR6
8
NDR7
NDR6
*1
NDRB
8
8
*1
NDRA
8
8
*2
TCSR
8
OVF
WT/IT
*2
TCNT
8
*3
RSTCSR
8
WRST
RSTOE —
SMR
8
C/A
CHR
BRR
8
SCR
8
TIE
RIE
TDR
8
SSR
8
TDRE
RDRF
RDR
8
2. For write access to TCSR and TCNT, see section 10.2.4, Notes on Register Access.
3. For write access to RSTCSR, see section 10.2.4, Notes on Register Access.
Serial communication interface
Bit Names
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
G3NOV G2NOV G1NOV G0NOV
NDR10 NDR9
NDR5
NDR4
NDR3
NDR2
NDR1
NDR5
NDR4
NDR11
NDR10 NDR9
NDR3
NDR2
NDR1
TME
CKS2
CKS1
PE
O/E
STOP
MP
CKS1
TE
RE
MPIE
TEIE
CKE1
ORER
FER
PER
TEND
MPB
478
Bit 0
Module Name
TPC
NDR8
NDR0
NDR8
NDR0
CKS0
WDT
CKS0
SCI channel 0
CKE0
MPBT
(Continued on next page)

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