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R8C/18 Group, R8C/19 Group
14.2.1
Timer Mode
In timer mode, a count source which is internally generated or timer X underflow is counted (refer to
Table 14.7 Timer Mode Specifications). The TZSC register is not used in timer mode. Figure 14.16
shows Registers TZMR and PUM in Timer Mode.
Table 14.7
Timer Mode Specifications
Item
Count sources
Count operations
Divided ratio
Count start condition
Count stop condition
Interrupt request
generation timing
TZOUT pin function
INT0 pin function
Read from timer
(1)
Write to timer
NOTE:
1. The IR bit in the TZIC register is set to 1 (interrupt requested) when writing to the TZPR or PREZ
register while both of the following conditions are met.
•
TZWC bit in TZMR register is set to 0 (write to reload register and counter simultaneously)
•
TZS bit in TZMR register is set to 1 (count starts)
Disable interrupts before writing to the TZPR or PREZ register in the above state.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
f1, f2, f8, Timer X underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues. (When timer Z underflows, the contents of timer Z primary
reload register is reloaded.)
1/(n+1)(m+1) fi: Count source frequency
n: Value set in PREZ register, m: value set in TZPR register
1 (count starts) is written to the TZS bit in the TZMR register.
0 (count stops) is written to the TZS bit in the TZMR register.
• When timer Z underflows [timer Z interrupt].
Programmable I/O port
Programmable I/O port, or INT0 interrupt input
The count value can be read out by reading registers TZPR and PREZ.
• When registers TZPR and PREZ are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TZPR and PREZ are written during the count while the TZWC
bit is set to 0 (writing to the reload register and counter simultaneously), the
value is written to each reload register of registers TZPR and PREZ at the
following count source input, the data is transferred to the counter at the
second count source input, and the count re-starts at the third count source
input.
When the TZWC bit is set to 1 (writing to only the reload register), the value is
written to each reload register of registers TZPR and PREZ (the data is
transferred to the counter at the following reload).
Page 122 of 233
Specification
14. Timers
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