Int0 Input Filter - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
12.2.2

INT0 Input Filter

The INT0 input contains a digital filter. The sampling clock is selected by bits INT0F1 to INT0F0 in
the INT0F register. The INT0 level is sampled every sampling clock cycle and if the sampled input
level matches three times, the IR bit in the INT0IC register is set to 1 (interrupt requested).
Figure 12.12 shows the Configuration of INT0 Input Filter. Figure 12.13 shows an Operating
Example of INT0 Input Filter.
INT0
Port P4_5
direction
register
INT0F0, INT0F1: Bits in INT0F register
INT0EN, INT0PL: Bits in INTEN register
Figure 12.12 Configuration of INT0 Input Filter
INT0 input
Sampling
timing
IR bit in
INT0IC register
This is an operating example in which bits INT0F1 to INT0F0 in the INT0F
register are set to 01b, 10b, or 11b (digital filter enabled).
Figure 12.13 Operating Example of INT0 Input Filter
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
INT0F1 to INT0F0
= 01b
f1
Sampling clock
= 10b
f8
= 11b
f32
Digital filter
(input level
matches 3x)
Page 86 of 233
INT0EN
Other than
INT0F1 to INT0F0
= 00b
= 00b
Both edges
detection
circuit
Set to 0 by a program
12. Interrupts
INT0 interrupt
INT0PL = 0
INT0PL = 1