Renesas R8C Series User Manual
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Renesas R8C Series User Manual

Renesas R8C Series User Manual

16-bit single-chip microcomputer
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On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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  • Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 4 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
  • Page 5 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
  • Page 6 The following documents apply to the R8C/1A Group, R8C/1B Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
  • Page 7 Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,”...
  • Page 8 Register Notation The symbols and terms used in register diagrams are described below. XXX Register Symbol Address After Reset Bit Symbol Bit Name Function b1 b0 XXX bits XXX0 1 0: XXX 0 1: XXX 1 0: Do not set. XXX1 1 1: XXX Nothing is assigned.
  • Page 9 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment bus Input/Output IrDA Infrared Data Association Least Significant Bit...

  • Page 10: Table Of Contents

    Table of Contents SFR Page Reference B - 1 Overview Applications ....................1 Performance Overview................2 Block Diagram .....................4 Product Information ..................5 Pin Assignments..................9 Pin Functions.....................12 Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3)............16 Address Registers (A0 and A1)..............16 Frame Base Register (FB) ................16 Interrupt Table Register (INTB) ..............16 Program Counter (PC) ................16...
  • Page 11 Special Function Registers (SFRs) Programmable I/O Ports Functions of Programmable I/O Ports ............24 Effect on Peripheral Functions ..............24 Pins Other than Programmable I/O Ports..........24 Port Settings....................32 Unassigned Pin Handling ................37 Resets Hardware Reset ..................40 6.1.1 When Power Supply is Stable ............40 6.1.2 Power On....................40 Power-On Reset Function .................42...
  • Page 12 10.3 CPU Clock and Peripheral Function Clock..........67 10.3.1 System Clock..................67 10.3.2 CPU Clock ..................67 10.3.3 Peripheral Function Clock (f1, f2, f4, f8, f32) ........67 10.3.4 fRING and fRING128................67 10.3.5 fRING-fast...................67 10.3.6 fRING-S ....................67 10.4 Power Control....................68 10.4.1 Standard Operating Mode ..............68 10.4.2 Wait Mode ..................69 10.4.3...
  • Page 13 12.4 Address Match Interrupt ................98 12.5 Notes on Interrupts..................100 12.5.1 Reading Address 00000h ..............100 12.5.2 SP Setting..................100 12.5.3 External Interrupt and Key Input Interrupt ........100 12.5.4 Watchdog Timer Interrupt..............100 12.5.5 Changing Interrupt Sources..............101 12.5.6 Changing Interrupt Control Register Contents .........102 13.
  • Page 14 15.1.3 Continuous Receive Mode ...............162 15.2 Clock Asynchronous Serial I/O (UART) Mode ........163 15.2.1 CNTR0 Pin Select Function..............166 15.2.2 Bit Rate.....................167 15.3 Notes on Serial Interface.................168 16. Clock Synchronous Serial Interface 16.1 Mode Selection..................169 16.2 Clock Synchronous Serial I/O with Chip Select (SSU)......170 16.2.1 Transfer Clock ..................179 16.2.2...
  • Page 15 18. Flash Memory 18.1 Overview ....................245 18.2 Memory Map ...................247 18.3 Functions to Prevent Rewriting of Flash Memory........249 18.3.1 ID Code Check Function ..............249 18.3.2 ROM Code Protect Function ............250 18.4 CPU Rewrite Mode..................251 18.4.1 EW0 Mode..................252 18.4.2 EW1 Mode..................252 18.4.3 Software Commands ................261 18.4.4...
  • Page 16 20.3.1 Notes on Timer X................300 20.3.2 Notes on Timer Z................300 20.3.3 Notes on Timer C ................301 20.4 Notes on Serial Interface.................302 20.5 Precautions on Clock Synchronous Serial Interface .......303 20.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ....303 20.5.2 Notes on I C bus Interface ...............304...
  • Page 17 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0000h 0040h 0001h 0041h 0002h 0042h 0003h 0043h 0004h Processor Mode Register 0 0044h 0005h Processor Mode Register 1 0045h 0006h System Clock Control Register 0 0046h 0007h System Clock Control Register 1 0047h 0008h 0048h...
  • Page 18 Address Register Symbol Page 0080h Timer Z Mode Register TZMR Address Register Symbol Page 0081h 00C0h A/D Register 0082h 00C1h 0083h 00C2h 0084h Timer Z Waveform Output Control Register 00C3h 0085h Prescaler Z Register PREZ 00C4h 0086h Timer Z Secondary Register TZSC 00C5h 0087h...

  • Page 19: Overview

    R8C/1A Group, R8C/1B Group REJ09B0252-0130 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.30 Dec 08, 2006 Overview These MCUs are fabricated using the high-performance silicon gate CMOS process, embedding the R8C/ Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic molded-HWQFN.

  • Page 20: Performance Overview

    20-pin molded-plastic SDIP 28-pin molded-plastic HWQFN NOTE: 1. I C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Please contact Renesas Technology sales offices for the Y version. Rev.1.30 Dec 08, 2006 Page 2 of 315 REJ09B0252-0130...
  • Page 21 20-pin molded-plastic SDIP 28-pin molded-plastic HWQFN NOTE: 1. I C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Please contact Renesas Technology sales offices for the Y version. Rev.1.30 Dec 08, 2006 Page 3 of 315 REJ09B0252-0130...

  • Page 22: Block Diagram

    R8C/1A Group, R8C/1B Group 1. Overview Block Diagram Figure 1.1 shows a Block Diagram. I/O ports Port P1 Port P3 Port P4 Peripheral Functions System clock generator Timers A/D converter × XIN-XOUT (10 bits 4 channels) High-speed on-chip oscillator Timer X (8 bits) UART or Low-speed on-chip Timer Z (8 bits)

  • Page 23: Product Information

    R8C/1A Group, R8C/1B Group 1. Overview Product Information Table 1.3 lists Product Information for R8C/1A Group and Table 1.4 lists Product Information for R8C/1B Group. Table 1.3 Product Information for R8C/1A Group Current of December 2006 Type No. ROM Capacity Package Type Remarks Capacity...
  • Page 24 R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors NOTE: Please contact Renesas Technology sales offices for the Y version. Figure 1.2 Type Number, Memory Size, and Package of R8C/1A Group Rev.1.30 Dec 08, 2006 Page 6 of 315...
  • Page 25 R8C/1A Group, R8C/1B Group 1. Overview Table 1.4 Product Information for R8C/1B Group Current of December 2006 ROM Capacity Type No. Package Type Remarks Capacity Program ROM Data Flash R5F211B1SP 4 Kbytes 1 Kbyte × 2 384 bytes PLSP0020JB-A R5F211B2SP 8 Kbytes 1 Kbyte ×...
  • Page 26 R8C/Tiny Series Memory Type F: Flash memory version Renesas MCU Renesas semiconductors NOTE: Please contact Renesas Technology sales offices for the Y version. Figure 1.3 Type Number, Memory Size, and Package of R8C/1B Group Rev.1.30 Dec 08, 2006 Page 8 of 315...

  • Page 27: Pin Assignments

    R8C/1A Group, R8C/1B Group 1. Overview Pin Assignments Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for PWQN0028KA-B Package (Top View). PIN assignments (top view) P3_5/SSCK/SCL/CMP1_2 P3_4/SCS/SDA/CMP1_1 P3_3/TCIN/INT3/SSI00/CMP1_0...
  • Page 28 R8C/1A Group, R8C/1B Group 1. Overview PIN assignments (top view) P3_5/SSCK/SCL/CMP1_2 P3_4/SCS/SDA/CMP1_1 P3_3/TCIN/INT3/SSI00/CMP1_0 P3_7/CNTR0/SSO/TXD1 P1_0/KI0/AN8/CMP0_0 RESET P1_1/KI1/AN9/CMP0_1 XOUT/P4_7 P4_2/VREF VSS/AVSS P1_2/KI2/AN10/CMP0_2 XIN/P4_6 P1_3/KI3/AN11/TZOUT VCC/AVCC P1_4/TXD0 MODE P1_5/RXD0/CNTR01/INT11 P4_5/INT0/RXD1 P1_6/CLK0/SSI01 P1_7/CNTR00/INT10 NOTE: 1. P4_7 is an input-only port. Package: PRDP0020BA-A (20P4B) Figure 1.5 Pin Assignments for PRDP0020BA-A Package (Top View) Rev.1.30...
  • Page 29 R8C/1A Group, R8C/1B Group 1. Overview PIN Assignment (top view) 21 20 19 18 17 16 15 P1_1/AN9/KI1/CMP0_1 P1_4/TXD0 P1_5/RXD0/CNTR01/INT11 P1_0/AN8/KI0/CMP0_0 P1_6/CLK0/SSI01 P3_3/TCIN/INT3/SSI00/CMP1_0 R8C/1A Group P1_7/CNTR00/INT10 P3_4/SCS/SDA/CMP1_1 R8C/1B Group P4_5/INT0/RXD1 P3_5/SSCK/SCL/CMP1_2 MODE P3_7/CNTR0/SSO/TXD1 VCC/AVCC RESET NOTES: 1. P4_7 is a port for the input. Package: PWQN0028KA-B(28PJW-B) Figure 1.6 Pin Assignments for PWQN0028KA-B Package (Top View)

  • Page 30: Pin Functions

    R8C/1A Group, R8C/1B Group 1. Overview Pin Functions Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KA- B Package. Table 1.5 Pin Functions Type...
  • Page 31 R8C/1A Group, R8C/1B Group 1. Overview Table 1.6 Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages I/O Pin Functions for Peripheral Modules Clock Control Port Serial Synchronous C bus Number Interrupt Timer Interface Serial I/O with Converter Interface Chip Select P3_5 CMP1_2...
  • Page 32 R8C/1A Group, R8C/1B Group 1. Overview Table 1.7 Pin Name Information by Pin Number of PWQN0028KA-B Package I/O Pin Functions for Peripheral Modules Clock Control Port Serial Synchronous C bus Number Interrupt Timer Interface Serial I/O with Converter Interface Chip Select XOUT P4_7 VSS/AVSS...

  • Page 33: Central Processing Unit (Cpu)

    R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b8b7 R0H (high-order of R0) R0L (low-order of R0)

  • Page 34: Data Registers (R0, R1, R2, And R3)

    R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.

  • Page 35: Interrupt Enable Flag (I)

    R8C/1A Group, R8C/1B Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.

  • Page 36: Memory

    R8C/1A Group, R8C/1B Group 3. Memory Memory R8C/1A Group Figure 3.1 is a Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16- Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.

  • Page 37: R8C/1B Group

    R8C/1A Group, R8C/1B Group 3. Memory R8C/1B Group Figure 3.2 is a Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.

  • Page 38: Special Function Registers (Sfrs)

    R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the special function registers. Table 4.1 SFR Information (1) Address Register Symbol...
  • Page 39 R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) Address Register Symbol After reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh Key Input Interrupt Control Register KUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADIC...
  • Page 40 R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Address Register Symbol After reset 0080h Timer Z Mode Register TZMR 0081h 0082h 0083h 0084h Timer Z Waveform Output Control Register 0085h Prescaler Z Register PREZ 0086h Timer Z Secondary Register TZSC...
  • Page 41 R8C/1A Group, R8C/1B Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Address Register Symbol After reset 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2...

  • Page 42: Programmable I/O Ports

    R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Programmable I/O Ports There are 13 programmable Input/Output ports (I/O ports) P1, P3_3 to P3_5, P3_7, and P4_5. 4_2 can be used as an input-only port. Also, P4_6 and P4_7 can be used as input-only ports if the main clock oscillation circuit is not used. Table 5.1 lists an Overview of Programmable I/O Ports.
  • Page 43 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports P1_0 to P1_3 Pull-up selection Direction register Output from individual peripheral function Data bus Port latch (Note 1) Drive capacity selection Input to individual peripheral function Analog input P1_4 Pull-up selection Direction register Output from individual peripheral function Data bus...
  • Page 44 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports P1_6, P1_7 Pull-up selection Direction register Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function P3_3 Pull-up selection Direction register Output from individual peripheral function Data bus Port latch (Note 1)
  • Page 45 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports P4_2 Vref of A/D converter (Note 4) Data bus P4_5 Pull-up selection Direction register Data bus Port latch (Note 4) Digital Input to individual peripheral function filter P4_6/XIN Data bus (Note 4) Clocked inverter (Note 2) P4_7/XOUT...
  • Page 46 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports MODE MODE signal input (Note 1) RESET RESET signal input (Note 1) NOTE : symbolizes a parasitic diode. Ensure the input voltage to each port will not exceed VCC. Figure 5.4 Configuration of I/O Pins Rev.1.30 Dec 08, 2006 Page 28 of 315...
  • Page 47 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports (1, 2) Port Pi Direction Register (i = 1, 3, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00E3h 00E7h 00EAh Bit Symbol Bit Name Function PDi_0 Port Pi0 direction bit 0 : Input mode (functions as an input port)
  • Page 48 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Port P4 Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00E8h Undefined Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0 (“L” level). —...
  • Page 49 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Pull-Up Control Register 0 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00FCh 00XX0000b PUR0 Bit Symbol Bit Name Function (b1-b0) Reserved bits Set to 0. PU02 P1_0 to P1_3 pull-up 0 : Not pulled up 1 : Pulled up PU03...

  • Page 50: Port Settings

    R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Port Settings Tables 5.4 to 5.17 list the port settings. Table 5.4 Port P1_0/KI0/AN8/CMP0_0 Register PUR0 KIEN ADCON0 TCOUT Function PD1_0 PU02 DRR0 KI0EN CH2, CH1, CH0, ADGSEL0 TCOUT0 P1_0 XXXXb Input port (not pulled up) XXXXb Input port (pulled up) XXXXb...
  • Page 51 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Table 5.7 Port P1_3/KI3/AN11/TZOUT Register PUR0 KIEN ADCON0 TZMR TZOC Function CH2, CH1, CH0, TZMOD1, PD1_3 PU02 DRR3 KI3EN TZOCNT ADGSEL0 TZMOD0 XXXXb Input port (not pulled up) XXXXb Input port (pulled up) XXXXb KI3 input 1111b...
  • Page 52 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Table 5.10 Port P1_6/CLK0/SSI01 SSU (Refer to Table 16.4 Association Register PUR0 U0MR between Communication Modes and I/O Pins ) Function SMD2, SMD1, PD1_6 PU03 SSI Output Control SSI Input Control SSISEL SMD0, CKDIR Other than 0X10b Input port (not pulled up)
  • Page 53 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Table 5.13 Port P3_4/SCS/SDA/CMP1_1 SSU (Refer to Table 16.4 Association between Register PUR0 TCOUT ICCR1 Communication Modes Function and I/O Pins ) SCS Output SCS Input PD3_4 PU07 TCOUT4 P3_4 Control Control Input port (not pulled up) Input port (pulled up) SCS input...
  • Page 54 R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Table 5.15 Port P3_7/CNTR0/SSO/TXD1 SSU (Refer to Table 16.4 Association between Register PUR0 U1MR TXMR UCON Communication Modes Function and I/O Pins ) SMD2, SSO Output SSO Input U1SEL1, PD3_7 PU07 TXOCNT SMD1, SMD0 Control Control...

  • Page 55: Unassigned Pin Handling

    R8C/1A Group, R8C/1B Group 5. Programmable I/O Ports Unassigned Pin Handling Table 5.18 lists Unassigned Pin Handling. Figure 5.11 shows Unassigned Pin Handling. Table 5.18 Unassigned Pin Handling Pin Name Connection Ports P1, P3_3 to P3_5, • After setting to input mode, connect each pin to VSS via a resistor (pull- P3_7, P4_5 down) or connect each pin to VCC via a resistor (pull-up).

  • Page 56: Resets

    R8C/1A Group, R8C/1B Group 6. Resets Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 6.1 lists the Reset Names and Sources. Table 6.1 Reset Names and Sources Reset Name Source...
  • Page 57 R8C/1A Group, R8C/1B Group 6. Resets Table 6.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 6.2 shows CPU Register Status after Reset and Figure 6.3 shows Reset Sequence. Table 6.2 Pin Functions while RESET Pin Level is “L” Pin Name Pin Functions Input port...

  • Page 58: Hardware Reset

    R8C/1A Group, R8C/1B Group 6. Resets Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are reset (refer to Table 6.2 Pin Functions while RESET Pin Level is “L”).
  • Page 59 R8C/1A Group, R8C/1B Group 6. Resets 2.7 V RESET RESET 0.2 VCC or below td(P-R) + 500 µs or more NOTE: 1. Refer to 19. Electrical Characteristics. Figure 6.4 Example of Hardware Reset Circuit and Operation Supply voltage detection circuit 2.7 V RESET RESET...

  • Page 60: Power-On Reset Function

    R8C/1A Group, R8C/1B Group 6. Resets Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor of about 5 kΩ, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, always keep the voltage to the RESET pin 0.8VCC or more.

  • Page 61: Voltage Monitor 1 Reset

    R8C/1A Group, R8C/1B Group 6. Resets Voltage Monitor 1 Reset A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset.

  • Page 62: Voltage Detection Circuit

    R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
  • Page 63 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit VCA27 Voltage detection 2 Noise filter signal Internal reference ≥ Vdet2 voltage VCA1 register VCA26 VCA13 bit Voltage detection 1 signal ≥ Vdet1 Figure 7.1 Block Diagram of Voltage Detection Circuit Voltage monitor 1 reset generation circuit VW1F1 to VW1F0 = 00b = 01b...
  • Page 64 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage monitor 2 interrupt/reset generation circuit VW2F1 to VW2F0 = 00b = 01b Voltage detection 2 circuit = 10b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. = 11b fRING-S When VCA27 bit is set to 0 (voltage...
  • Page 65 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 0031h 00001000b VCA1 Bit Symbol Bit Name Function — Reserved bits Set to 0. (b2-b0) Voltage detection 2 signal monitor 0 : VCC <...
  • Page 66 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage Monitor 1 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset VW1C 0036h Hardw are reset : 0000X000b Pow er-on reset, voltage monitor 1 reset : 0100X001b Bit Symbol Bit Name...
  • Page 67 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage Monitor 2 Circuit Control Register b7 b6 b5 b4 b1 b0 Symbol Address After Reset VW2C 0037h Bit Symbol Bit Name Function Voltage monitor 2 interrupt / 0 : Disable VW2C0 (6, 10) reset enable bit 1 : Enable...

  • Page 68: Vcc Input Voltage

    R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit VCC Input Voltage 7.1.1 Monitoring Vdet1 Vdet1 cannot be monitored. 7.1.2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 19.
  • Page 69 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage monitor 1 reset Vdet1 Sampling timing Internal reset signal Sampling clock of digital filter x 4 cycles Operation when the VW1C1 bit in the VW1C register is set to 0 (digital filter enabled) Voltage monitor 2 interrupt Vdet2 Sampling...

  • Page 70: Voltage Monitor 1 Reset

    R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage Monitor 1 Reset Table 7.2 lists the Setting Procedure of Voltage Monitor 1 Reset Associated Bits and Figure 7.8 shows an Operating Example of Voltage Monitor 1 Reset. To use voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled).

  • Page 71: Voltage Monitor 2 Interrupt And Voltage Monitor 2 Reset

    R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 7.3 lists the Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bits. Figure 7.9 shows an Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset. To use voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled).
  • Page 72 R8C/1A Group, R8C/1B Group 7. Voltage Detection Circuit Vdet2 (Typ. 3.30 V) 2.7 V VCA13 bit Sampling clock of digital filter Sampling clock of digital filter x 4 cycles x 4 cycles VW2C2 bit Set to 0 by a program When the VW2C1 bit is set Set to 0 by interrupt request to 0 (digital filter enabled).

  • Page 73: Processor Mode

    R8C/1A Group, R8C/1B Group 8. Processor Mode Processor Mode Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table 8.1 Features of Processor Mode Processor Mode...
  • Page 74 R8C/1A Group, R8C/1B Group 8. Processor Mode Processor Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0005h Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. — (b0) When read, the content is undefined.

  • Page 75: Bus

    R8C/1A Group, R8C/1B Group 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/1A Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/1B Group. ROM/RAM and SFR are connected to the CPU by an 8-bit bus.

  • Page 76: 10. Clock Generation Circuit

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10. Clock Generation Circuit The clock generation circuit has: • Main clock oscillation circuit • On-chip oscillator (oscillation stop detection function) Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures 9.2 to 10.5 show clock associated registers.
  • Page 77 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit HRA1 register HRA2 register On-chip oscillator clock Frequency adjustable High-speed fRING-fast HRA00 C bus on-chip Watchdog oscillator timer UART1 fRING128 fRING HRA01 = 1 1/128 Timer C INT0 Timer X Timer Z UART0 Converter HRA01 = 0...
  • Page 78 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0006h Bit Symbol Bit Name Function — Reserved bits Set to 0. (b1-b0) WAIT peripheral function clock stop 0 : Peripheral function clock does not stop in w ait mode.
  • Page 79 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit System Clock Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0007h Bit Symbol Bit Name Function (4,7,8) All clock stop control bit 0 : Clock operates. CM10 1 : Stops all clocks (stop mode).
  • Page 80 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 000Ch Bit Symbol Bit Name Function Oscillation stop detection enable b1 b0 bits 0 0 : Oscillation stop detection function OCD0...
  • Page 81 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Symbol Address After Reset 0020h HRA0 Bit Symbol Bit Name Function High-speed on-chip oscillator enable 0 : High-speed on-chip oscillator off HRA00 1 : High-speed on-chip oscillator on...
  • Page 82 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0021h HRA1 When Shipping Function The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7. High-speed on-chip oscillator frequency = 8 MHz (HRA1 register = value w hen shipping ;...

  • Page 83: Main Clock

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit The clocks generated by the clock generation circuits are described below. 10.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.

  • Page 84: On-Chip Oscillator Clocks

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.2 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register. 10.2.1 Low-Speed On-Chip Oscillator Clock The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,...

  • Page 85: Cpu Clock And Peripheral Function Clock

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.3 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. 10.3.1 System Clock The system clock is the clock source for the CPU and peripheral function clocks.

  • Page 86: Power Control

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.4 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 10.4.1 Standard Operating Mode Standard operating mode is further separated into four modes. In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks.

  • Page 87: Wait Mode

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.4.1.1 High-Speed Mode The main clock divided by 1 (no division) provides the CPU clock. If the CM14 bit is set to 0 (low-speed on- chip oscillator on) or the HRA00 bit in the HRA0 register is set to 1 (high-speed on-chip oscillator on), fRING and fRING128 can be used as timers X and C.
  • Page 88 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.4.2.4 Exiting Wait Mode The MCU exits wait mode by a hardware reset or a peripheral function interrupt. To use a hardware reset to exit wait mode, set bits ILVL2 to ILVL0 for the peripheral function interrupts to 000b (interrupts disabled) before executing the WAIT instruction.
  • Page 89 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit Figure 10.8 shows the Time from Wait Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode.

  • Page 90: Stop Mode

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.4.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in stop mode.
  • Page 91 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit FMR0 Register Time until Flash Memory Time until CPU Clock Time for Interrupt Remarks is Activated (T2) is Supplied (T3) Sequence (T4) FMSTP Bit Period of CPU clock Period of system clock Period of CPU clock Following total time is ×...

  • Page 92: Oscillation Stop Detection Function

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.5 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the main clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by bits OCD1 to OCD0 in the OCD register. Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
  • Page 93 R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, and Voltage Monitor 2 Interrupts Generated Interrupt Source Bit Showing Interrupt Cause Oscillation stop detection (a) OCD3 bit in OCD register = 1 ( (a) or (b) ) (b) Bits OCD1 to OCD0 in OCD register = 11b and OCD2 bit = 1 Watchdog timer...

  • Page 94: Notes On Clock Generation Circuit

    R8C/1A Group, R8C/1B Group 10. Clock Generation Circuit 10.6 Notes on Clock Generation Circuit 10.6.1 Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops.

  • Page 95: 11. Protection

    R8C/1A Group, R8C/1B Group 11. Protection 11. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. •...

  • Page 96: 12. Interrupts

    R8C/1A Group, R8C/1B Group 12. Interrupts 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the types of Interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (non-maskable interrupt) INT instruction Interrupt Watchdog timer Oscillation stop detection Special Voltage monitor 2 (non-maskable interrupt)

  • Page 97: Software Interrupts

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed.

  • Page 98: Special Interrupts

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. Reset the watchdog timer after the watchdog timer interrupt is generated. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt The oscillation stop detection interrupt is generated by the oscillation stop detection function.

  • Page 99: Interrupts And Interrupt Vectors

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows an Interrupt Vector.
  • Page 100 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Software Vector Address Interrupt Source Reference...

  • Page 101: Interrupt Control

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or disable maskable interrupts.
  • Page 102 R8C/1A Group, R8C/1B Group 12. Interrupts INT0 Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 005Dh XX00X000b INT0IC Bit Symbol Bit Name Function b2 b1 b0 Interrupt priority level select bits 0 0 0 : Level 0 (interrupt disable) ILVL0 0 0 1 : Level 1 0 1 0 : Level 2...
  • Page 103 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR Bit The IR bit is set to 1 (interrupt requested) when an interrupt request is generated.
  • Page 104 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level after the instruction is completed.
  • Page 105 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6.5 Interrupt Response Time Figure 12.6 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt response time includes the period between interrupt request generation and the completion of execution of the instruction (refer to (a) in Figure 12.6) and the period required to perform the interrupt sequence (20 cycles, see (b) in Figure 12.6).
  • Page 106 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved to the stack, the 16 low-order bits in the PC are saved.
  • Page 107 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, that was running before the interrupt request was acknowledged, starts running again.
  • Page 108 R8C/1A Group, R8C/1B Group 12. Interrupts 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.10. Priority level of each interrupt Highest Level 0 (default value) Compare 0 INT3 Timer Z Timer X INT0 Timer C...

  • Page 109: Int Interrupt

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.2 INT Interrupt 12.2.1 INT0 Interrupt The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in the INTEN register is set to 1 (enable). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register.

  • Page 110: Int0 Input Filter

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.2.2 INT0 Input Filter The INT0 input contains a digital filter. The sampling clock is selected by bits INT0F1 to INT0F0 in the INT0F register. The INT0 level is sampled every sampling clock cycle and if the sampled input level matches three times, the IR bit in the INT0IC register is set to 1 (interrupt requested).

  • Page 111: Int1 Interrupt

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.2.3 INT1 Interrupt The INT1 interrupt is generated by an INT1 input. The edge polarity is selected by the R0EDG bit in the TXMR register. When the CNTRSEL bit in the UCON register is set to 0, the INT10 pin becomes the INT1 input pin. When the CNTRSEL bit is set to 1, the INT11 pin becomes the INT1 input pin.

  • Page 112: Int3 Interrupt

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.2.4 INT3 Interrupt The INT3 interrupt is generated by an INT3 input. Set the TCC07 bit in the TCC0 register to 0 (INT3). When the TCC06 bit in the TCC0 register is set to 0, an INT3 interrupt request is generated in synchronization with the count source of timer C.
  • Page 113 R8C/1A Group, R8C/1B Group 12. Interrupts Timer C Control Register 1 b7 b6 b5 b4 b3 b2 Symbol Address After Reset 009Bh TCC1 Bit Symbol Bit Name Function _____ INT3 filter select bits b1b0 TCC10 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling TCC11...

  • Page 114: Key Input Interrupt

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i = 0 to 3) bit in the KIEN register can select whether or not the pins are used as KIi input.
  • Page 115 R8C/1A Group, R8C/1B Group 12. Interrupts Key Input Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0098h KIEN Bit Symbol Bit Name Function KI0 input enable bit 0 : Disable KI0EN 1 : Enable KI0 input polarity select bit 0 : Falling edge KI0PL...

  • Page 116: Address Match Interrupt

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register (i = 0, 1). This interrupt is used as a break function by the debugger. When using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system.
  • Page 117 R8C/1A Group, R8C/1B Group 12. Interrupts Address Match Interrupt Enable Register b7 b6 b5 b4 b2 b1 b0 Symbol Address After Reset 0009h AIER Bit Symbol Bit Name Function Address match interrupt 0 enable bit 0 : Disable AIER0 1 : Enable Address match interrupt 1 enable bit 0 : Disable AIER1...

  • Page 118: Notes On Interrupts

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.5 Notes on Interrupts 12.5.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0.

  • Page 119: Changing Interrupt Sources

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.5.5 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing.

  • Page 120: Changing Interrupt Control Register Contents

    R8C/1A Group, R8C/1B Group 12. Interrupts 12.5.6 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents.

  • Page 121: 13. Watchdog Timer

    R8C/1A Group, R8C/1B Group 13. Watchdog Timer 13. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable.
  • Page 122 R8C/1A Group, R8C/1B Group 13. Watchdog Timer Option Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol Address Before Shipment 0FFFFh Bit Symbol Bit Name Function Watchdog timer start 0 : Starts w atchdog timer automatically after reset. select bit 1 : Watchdog timer is inactive after reset.
  • Page 123 R8C/1A Group, R8C/1B Group 13. Watchdog Timer Watchdog Timer Reset Register Symbol Address After Reset 000Dh Undefined WDTR Function When 00h is w ritten before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is 7FFFh w hen count source protection mode is disabled and 0FFFh w hen count source protection mode is enabled.

  • Page 124: Count Source Protection Mode Disabled

    R8C/1A Group, R8C/1B Group 13. Watchdog Timer 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled). Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled) Item...

  • Page 125: Count Source Protection Mode Enabled

    R8C/1A Group, R8C/1B Group 13. Watchdog Timer 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the watchdog timer.

  • Page 126: 14. Timers

    R8C/1A Group, R8C/1B Group 14. Timers 14. Timers The MCU has two 8-bit timers with 8-bit prescalers, and a 16-bit timer. The two 8-bit timers with 8-bit prescalers are timer X and timer Z. These timers contain a reload register to store the default value of the counter. The 16-bit timer is timer C, and has input capture and output compare functions.

  • Page 127: Timer X

    R8C/1A Group, R8C/1B Group 14. Timers 14.1 Timer X Timer X is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers PREX and TX (refer to Tables 14.2 to 14.6 the Specifications of Each Mode).
  • Page 128 R8C/1A Group, R8C/1B Group 14. Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 008Bh TXMR Bit Symbol Bit Name Function Operating mode select bits 0, 1 b1 b0 0 0 : Timer mode or pulse period measurement TXMOD0 mode 0 1 : Pulse output mode...
  • Page 129 R8C/1A Group, R8C/1B Group 14. Timers Prescaler X Register Symbol Address After Reset 008Ch PREX Mode Function Setting Range Timer mode Counts internal count source. 00h to FFh Pulse output mode Counts internal count source. 00h to FFh Counts input pulses from external clock. Event counter mode 00h to FFh Measures pulse w idth of input pulses from...

  • Page 130: Timer Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode Specifications). Figure 14.4 shows the TXMR Register in Timer Mode. Table 14.2 Timer Mode Specifications Item Specification Count sources...

  • Page 131: Pulse Output Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the CNTR0 pin each time the timer underflows (refer to Table 14.3 Pulse Output Mode Specifications).
  • Page 132 R8C/1A Group, R8C/1B Group 14. Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol Address After Reset 008Bh TXMR Bit Symbol Bit Name Function Operating mode select bits 0, 1 b1 b0 TXMOD0 0 1 : Pulse output mode TXMOD1...

  • Page 133: Event Counter Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/CNTR0 pin are counted (refer to Table 14.4 Event Counter Mode Specifications). Figure 14.6 shows the TXMR Register in Event Counter Mode. Table 14.4 Event Counter Mode Specifications Item...

  • Page 134: Pulse Width Measurement Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/CNTR0 pin is measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.7 shows the TXMR Register in Pulse Width Measurement Mode.
  • Page 135 R8C/1A Group, R8C/1B Group 14. Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 0 0 0 0 Symbol Address After Reset 008Bh TXMR Bit Symbol Bit Name Function TXMOD0 Operating mode select bits 0, 1 b1 b0 1 1 : Pulse w idth measurement mode TXMOD1 _____...
  • Page 136 R8C/1A Group, R8C/1B Group 14. Timers n = high level: the contents of TX register, low level: the contents of PREX register FFFFh Count start Underflow Count stop Count stop Count start 0000h Period Set to 1 by program TXS bit in TXMR register Measured pulse (CNTR0i pin input)

  • Page 137: Pulse Period Measurement Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1/CNTR0 pin is measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.9 shows the TXMR Register in Pulse Period Measurement Mode.
  • Page 138 R8C/1A Group, R8C/1B Group 14. Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 008Bh TXMR Bit Symbol Bit Name Function Operating mode select bits 0, 1 b1 b0 TXMOD0 0 0 : Timer mode or pulse period measurement mode TXMOD1 _____...
  • Page 139 R8C/1A Group, R8C/1B Group 14. Timers Underflow signal of prescaler X Set to 1 by program TXS bit in TXMR register Starts counting CNTR0i pin input Timer X Timer X Timer X reloads reloads reloads Contents of timer X 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh Retained Retained...

  • Page 140: Notes On Timer X

    R8C/1A Group, R8C/1B Group 14. Timers 14.1.6 Notes on Timer X • Timer X stops counting after a reset. Set the values in the timer and prescaler before the count starts. • Even if the prescaler and timer are read out in 16-bit units, these registers are read 1 byte at a time by the MCU.

  • Page 141: Timer Z

    R8C/1A Group, R8C/1B Group 14. Timers 14.2 Timer Z Timer Z is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address. Refer to the Tables 14.7 to 14.10 for the Specifications of Each Mode.
  • Page 142 R8C/1A Group, R8C/1B Group 14. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0080h TZMR Bit Symbol Bit Name Function — Reserved bits Set to 0. (b3-b0) Timer Z operating mode b5 b4 bits 0 0 : Timer mode...
  • Page 143 R8C/1A Group, R8C/1B Group 14. Timers Prescaler Z Register Symbol Address After Reset 0085h PREZ Mode Function Setting Range Counts internal count source or timer X 00h to FFh Timer mode underflow s. Programmable w aveform Counts internal count source or timer X 00h to FFh generation mode underflow s.
  • Page 144 R8C/1A Group, R8C/1B Group 14. Timers Timer Z Output Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 008Ah TZOC Bit Symbol Bit Name Function Timer Z one-shot start bit 0 : One-shot stops. TZOS 1 : One-shot starts.
  • Page 145 R8C/1A Group, R8C/1B Group 14. Timers Timer Count Source Setting Register b7 b6 b5 b4 b2 b1 b0 Symbol Address After Reset 008Eh TCSS Bit Symbol Bit Name Function Timer X count source select bits b1 b0 TXCK0 0 0 : f1 0 1 : f8 1 0 : fRING TXCK1...

  • Page 146: Timer Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.2.1 Timer Mode In timer mode, a count source which is internally generated or timer X underflow is counted (refer to Table 14.7 Timer Mode Specifications). The TZSC register is not used in timer mode. Figure 14.16 shows Registers TZMR and PUM in Timer Mode.
  • Page 147 R8C/1A Group, R8C/1B Group 14. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 0080h TZMR Bit Symbol Bit Name Function — Reserved bits Set to 0. (b3-b0) TZMOD0 Timer Z operating mode b5 b4 0 0 : Timer mode bits...

  • Page 148: Programmable Waveform Generation Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.2.2 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TZOUT pin is inverted each time the counter underflows, while the values in registers TZPR and TZSC are counted alternately (refer to Table 14.8 Programmable Waveform Generation Mode Specifications).
  • Page 149 R8C/1A Group, R8C/1B Group 14. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 0 0 0 Symbol Address After Reset 0080h TZMR Bit Symbol Bit Name Function — Reserved bits Set to 0. (b3-b0) b5 b4 TZMOD0...
  • Page 150 R8C/1A Group, R8C/1B Group 14. Timers Set to 1 by program TZS bit in TZMR register Count source Prescaler Z underflow signal Timer Z Timer Z secondary primary reloads reloads Contents of timer Z Set to 0 when interrupt request is acknowledged, or set by program IR bit in...

  • Page 151: Programmable One-Shot Generation Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.2.3 Programmable One-shot Generation Mode In programmable one-shot generation mode, one-shot pulse is output from the TZOUT pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable One-Shot Generation Mode Specifications).
  • Page 152 R8C/1A Group, R8C/1B Group 14. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 1 1 0 Symbol Address After Reset 0080h TZMR Bit Symbol Bit Name Function — Reserved bits Set to 0. (b3-b0) TZMOD0 Timer Z operating mode bit b5 b4 1 0 : Programmable one-shot generation mode TZMOD1...
  • Page 153 R8C/1A Group, R8C/1B Group 14. Timers Set to 1 by program TZS bit in TZMR register Set to 0 when Set to 1 by INT0 pin Set to 1 by program counting ends input trigger TZOS bit in TZOC register Count source Prescaler Z underflow signal...

  • Page 154: Programmable Wait One-Shot Generation Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.2.4 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TZOUT pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable Wait One-Shot Generation Mode Specifications).
  • Page 155 R8C/1A Group, R8C/1B Group 14. Timers Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Item Specification Count sources f1, f2, f8, Timer X underflow Count operations • Decrement the value set in Timer Z primary • When the count of TZPR register underflows, the timer reloads the contents of the TZSC register before the count is continued.
  • Page 156 R8C/1A Group, R8C/1B Group 14. Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 b1 1 1 1 Symbol Address After Reset 0080h TZMR Bit Symbol Bit Name Function — Reserved bits Set to 0. (b3-b0) Timer Z operating mode b5 b4 TZMOD0 bits...
  • Page 157 R8C/1A Group, R8C/1B Group 14. Timers Set to 1 by program TZS bit in TZMR register Set to 1 by program, or set to 1 by INT0 pin Set to 0 when input trigger counting ends TZOS bit in TZOC register Count source Prescaler Z underflow...

  • Page 158: Notes On Timer Z

    R8C/1A Group, R8C/1B Group 14. Timers 14.2.5 Notes on Timer Z • Timer Z stops counting after a reset. Set the values in the timer and prescaler before the count starts. • Even if the prescaler and timer are read out in 16-bit units, these registers are read 1 byte at a time by the MCU.

  • Page 159: Timer C

    R8C/1A Group, R8C/1B Group 14. Timers 14.3 Timer C Timer C is a 16-bit timer. Figure 14.23 shows a Block Diagram of Timer C. Figure 14.24 shows a Block Diagram of CMP Waveform Generation Unit. Figure 14.25 shows a Block Diagram of CMP Waveform Output Unit. Timer C has two modes: input capture mode and output compare mode.
  • Page 160 R8C/1A Group, R8C/1B Group 14. Timers TCC14 TCC15 Compare 0 interrupt signal Compare 1 interrupt signal TCC16 TCC17 TCC17 to TCC16 “H” CMP output = 11b “L” Latch (internal signal) = 10b Reverse = 01b Reset TCC15 to TCC14 Reverse = 01b “L”...
  • Page 161 R8C/1A Group, R8C/1B Group 14. Timers Timer C Register (b15) (b8) Symbol Address After Reset 0091h-0090h 0000h Function Counts internal count source. 0000h can be read w hen the TCC00 bit is set to 0 (count stops). Count value can be read w hen the TCC00 bit is set to 1 (count starts). Capture and Compare 0 Register (b15) (b8)
  • Page 162 R8C/1A Group, R8C/1B Group 14. Timers Timer C Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 009Ah TCC0 Bit Symbol Bit Name Function Timer C count start bit 0 : Stops counting. TCC00 1 : Starts counting.
  • Page 163 R8C/1A Group, R8C/1B Group 14. Timers Timer C Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 009Bh TCC1 Bit Symbol Bit Name Function _____ INT3 filter select bits b1 b0 TCC10 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling TCC11...
  • Page 164 R8C/1A Group, R8C/1B Group 14. Timers Timer C Output Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol A ddress A f ter Reset 00FFh TCOUT Bit Symbol Bit Name Function CMP output enable bit 0 0 : Disables CMP output f rom CMP0_0. TCOUT0 1 : Enables CMP output f rom CMP0_0.

  • Page 165: Input Capture Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.3.1 Input Capture Mode In input capture mode, the edge of the TCIN pin input signal or the fRING128 clock is used as a trigger to latch the timer value and generate an interrupt request. The TCIN input contains a digital filter, and this prevents errors caused by noise or the like from occurring.
  • Page 166 R8C/1A Group, R8C/1B Group 14. Timers FFFFh Overflow Count starts ← Measurement value 2 ← Measurement ← Measurement value1 value3 0000h Time Set to 0 by Set to 1 by program program TCC00 bit in TCC0 register The delay caused by digital filter and one count source cycle delay (max.) Measured pulse (TCIN pin input)

  • Page 167: Output Compare Mode

    R8C/1A Group, R8C/1B Group 14. Timers 14.3.2 Output Compare Mode In output compare mode, an interrupt request is generated when the value of the TC register matches the value of the TM0 or TM1 register. Table 14.12 shows the Output Compare Mode Specifications. Figure 14.31 shows an Operating Example in Output Compare Mode.
  • Page 168 R8C/1A Group, R8C/1B Group 14. Timers Match Value set in TM1 register Count starts Match Match Value set in TM0 register 0000h Time Set to 1 by program TCC00 bit in TCC0 register Set to 0 when interrupt request is acknowledged, or set by program IR bit in CMP0IC register Set to 0 when interrupt request is...

  • Page 169: Notes On Timer C

    R8C/1A Group, R8C/1B Group 14. Timers 14.3.3 Notes on Timer C Access registers TC, TM0, and TM1 in 16-bit units. The TC register can be read in 16-bit units. This prevents the timer value from being updated between when the low-order bytes and high-order bytes are being read.

  • Page 170: 15. Serial Interface

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15. Serial Interface The serial interface consists of two channels (UART0 and UART1). Each UARTi (i = 0 or 1) has an exclusive timer to generate the transfer clock and operates independently. Figure 15.1 shows a UARTi (i = 0 or 1) Block Diagram. Figure 15.2 shows a UARTi Transmit/Receive Unit. UART0 has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
  • Page 171 R8C/1A Group, R8C/1B Group 15. Serial Interface Clock synchronous type PRYE = 0 Clock UART (7 bits) synchronous disabled UART (7 bits) UARTi receive register UART (8 bits) type RXDi Clock UART UART (9 bits) enabled synchronous PRYE = 1 type UART (8 bits) UART (9 bits)
  • Page 172 R8C/1A Group, R8C/1B Group 15. Serial Interface (1, 2) UARTi Transmit Buffer Register (i = 0 or 1) (b15) (b8) Symbol Address After Reset 00A3h-00A2h Undefined U0TB 00ABh-00AAh Undefined U1TB Bit Symbol Function — Transmit data (b8-b0) — Nothing is assigned. If necessary, set to 0. —...
  • Page 173 R8C/1A Group, R8C/1B Group 15. Serial Interface UARTi Transmit / Receive Mode Register (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset U0MR 00A0h U1MR 00A8h Bit Symbol Bit Name Function Serial interface mode select b2 b1 b0 SMD0 bits...
  • Page 174 R8C/1A Group, R8C/1B Group 15. Serial Interface UARTi Transmit / Receive Control Register 0 (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00A4h U0C0 00ACh U1C0 Bit Symbol Bit Name Function BRG count source select b1 b0 bits...
  • Page 175 R8C/1A Group, R8C/1B Group 15. Serial Interface UARTi Transmit / Receive Control Register 1 (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U0C1 00A5h U1C1 00ADh Bit Symbol Bit Name Function Transmit enable bit 0 : Disables transmission.

  • Page 176: Clock Synchronous Serial I/O Mode

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15.1 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode Table 15.1 Clock Synchronous Serial I/O Mode Specifications...
  • Page 177 R8C/1A Group, R8C/1B Group 15. Serial Interface Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Function U0TB 0 to 7 Set data transmission. U0RB 0 to 7 Data reception can be read. Overrun error flag U0BRG 0 to 7 Set bit rate.
  • Page 178 R8C/1A Group, R8C/1B Group 15. Serial Interface • Example of transmit timing (when internal clock is selected) Transfer clock TE bit in U0C1 register Set data in U0TB register TI bit in U0C1 register Transfer from U0TB register to UART0 transmit register TCLK Pulse stops because the TE bit is set to 0 CLK0...

  • Page 179: Polarity Select Function

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15.1.1 Polarity Select Function Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. • When the CKPOL bit in the U0C0 register = 0 (output transmit data at the falling edge and input the receive data at the rising edge of the transfer clock) CLK0 TXD0...

  • Page 180: Continuous Receive Mode

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15.1.3 Continuous Receive Mode Continuous receive mode is selected by setting the U0RRM bit in the UCON register to 1 (enables continuous receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data in the U0TB register).

  • Page 181: Clock Asynchronous Serial I/O (Uart) Mode

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format. Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode. Table 15.4 UART Mode Specifications Item...
  • Page 182 R8C/1A Group, R8C/1B Group 15. Serial Interface Table 15.5 Registers Used and Settings for UART Mode Register Function UiTB 0 to 8 Set transmit data. UiRB 0 to 8 Receive data can be read. OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a bit rate.
  • Page 183 R8C/1A Group, R8C/1B Group 15. Serial Interface • Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) Transfer clock TE bit in UiC1 register Write data to UiTB register TI bit in UiC1 register Stop pulsing Transfer from UiTB register to UARTi transmit register because the TE bit is set to 0 Start...

  • Page 184: Cntr0 Pin Select Function

    R8C/1A Group, R8C/1B Group 15. Serial Interface • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG output UiC1 register RE bit Stop bit Start bit RXDi Determined to be “L” Receive data taken in Transfer clock Reception triggered when transfer clock Transferred from UARTi receive...

  • Page 185: Bit Rate

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15.2.2 Bit Rate In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register. UART Mode • Internal clock selected UiBRG register setting value = Bit Rate ×...

  • Page 186: Notes On Serial Interface

    R8C/1A Group, R8C/1B Group 15. Serial Interface 15.3 Notes on Serial Interface • When reading data from the UiRB register either in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.

  • Page 187: 16. Clock Synchronous Serial Interface

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock synchronous serial interface Clock synchronous serial I/O with chip select (SSU) Clock synchronous communication mode 4-wire bus communication mode C bus Interface C bus interface mode Clock synchronous serial mode...

  • Page 188: Clock Synchronous Serial I/O With Chip Select (Ssu)

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) Clock synchronous serial I/O with chip select supports clock synchronous serial data communication. Table 16.2 shows a Clock Synchronous Serial I/O with Chip Select Specifications and Figure 16.1 shows a Block Diagram of Clock Synchronous Serial I/O with Chip Select.
  • Page 189 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Internal clock (f1/i) Internal clock generation circuit Multiplexer SSCK SSMR register SSCRL register SSCRH register Transmit/receive SSER register control circuit SSSR register SSMR2 register SSTDR register SSTRSR register Selector SSRDR register Interrupt requests (TXI, TEI, RXI, OEI, and CEI) i = 4, 8, 16, 32, 64, 128, or 256...
  • Page 190 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Control Register H b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00B8h SSCRH Bit Symbol Bit Name Function Transfer clock rate select bits b2 b1 b0 0 0 0 : f1/256 CKS0 0 0 1 : f1/128...
  • Page 191 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Control Register L b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00B9h 01111101b SSCRL Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. —...
  • Page 192 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00BAh 00011000b SSMR Bit Symbol Bit Name Function Bit counter 2 to 0 b2 b1 b0 0 0 0 : 8 bits left 0 0 1 : 1 bit left 0 1 0 : 2 bits left...
  • Page 193 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Enable Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BBh SSER Bit Symbol Bit Name Function Conflict error interrupt enable bit 0 : Disables conflict error interrupt request. CEIE 1 : Enables conflict error interrupt request.
  • Page 194 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Status Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BCh SSSR Bit Symbol Bit Name Function Conflict error flag 0 : No conflict errors generated 1 : Conflict errors generated —...
  • Page 195 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Mode Register 2 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BDh SSMR2 Bit Symbol Bit Name Function Clock synchronous serial I/O w ith 0 : Clock synchronous communication mode chip select mode select bit 1 : Four-w ire bus communication mode SSUMS...
  • Page 196 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SS Transmit Data Register b7 b6 b5 b4 Symbol Address After Reset 00BEh SSTDR Function Store the transmit data. The stored transmit data is transferred to the SSTRSR register and transmission is started w hen it is detected that the SSTRSR register is empty.

  • Page 197: Transfer Clock

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.1 Transfer Clock The transfer clock can be selected among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4) and an external clock. When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin.
  • Page 198 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface • SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge), and CPOS bit = 0 (“H” when clock stops) SSCK SSO, SSI • SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge) SSCK CPOS = 0 (“H”...

  • Page 199: Ss Shift Register (Sstrsr)

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.2 SS Shift Register (SSTRSR) The SSTRSR register is a shift register for transmitting and receiving serial data. When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register.

  • Page 200: Interrupt Requests

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.3 Interrupt Requests Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.

  • Page 201: Communication Modes And Pin Functions

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.4 Communication Modes and Pin Functions Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register. Table 16.4 shows the Association between Communication Modes and I/O Pins.

  • Page 202: Clock Synchronous Communication Mode

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.5 Clock Synchronous Communication Mode 16.2.5.1 Initialization in Clock Synchronous Communication Mode Figure 16.12 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or reception.
  • Page 203 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.5.2 Data Transmission Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Transmission (Clock Synchronous Communication Mode). During data transmission, clock synchronous serial I/O with chip select operates as described below. When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and data.
  • Page 204 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Start Initialization (1) After reading the SSSR register and confirming Read TDRE bit in SSSR register that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0.
  • Page 205 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.5.3 Data Reception Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Reception (Clock Synchronous Communication Mode). During data reception clock synchronous serial I/O with chip select operates as described below. When clock synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and inputs data.
  • Page 206 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Start Initialization (1) After setting each register in the clock synchronous Dummy read of SSRDR register serial I/O with chip select register, a dummy read of the SSRDR register is performed and the receive operation is started.
  • Page 207 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.5.4 Data Transmission/Reception Data transmission/reception is an operation combining data transmission and reception, which were described earlier. Transmission/reception is started by writing data to the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
  • Page 208 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Start Initialization (1) After reading the SSSR register and confirming Read TDRE bit in SSSR register that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0.

  • Page 209: Operation In 4-Wire Bus Communication Mode

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.6 Operation in 4-Wire Bus Communication Mode In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication. This mode includes bidirectional mode in which the data input line and data output line function as a single pin.
  • Page 210 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Start RE bit ← 0 SSER register TE bit ← 0 SSUMS bit ← 1 SSMR2 register (1) The MLS bit is set to 0 for MSB-first transfer. SSMR register Set bits CPHS and CPOS MLS bits ←...
  • Page 211 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.6.2 Data Transmission Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Transmission (4-Wire Bus Communication Mode). During the data transmit operation, clock synchronous serial I/O with chip select operates as described below.
  • Page 212 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface • CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops) High-impedance (output) SSCK 1 frame 1 frame TDRE bit in SSSR register TEI interrupt request is generated TXI interrupt request is...
  • Page 213 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.6.3 Data Reception Figure 16.20 shows an example of clock synchronous serial I/O with chip select operation (4-wire bus communication mode) for data reception. During data reception, clock synchronous serial I/O with chip select operates as described below.
  • Page 214 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface • CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops) High-impedance (output) SSCK 1 frame 1 frame RDRF bit in SSSR register RXI interrupt request RXI interrupt request RSSTP bit in...

  • Page 215: Scs Pin Control And Arbitration

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.7 SCS Pin Control and Arbitration When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode).and the CSS1 bit in the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as the master device) and check the arbitration of the SCS pin before starting serial transfer.

  • Page 216: Notes On Clock Synchronous Serial I/O With Chip Select

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select function.

  • Page 217: I 2 C Bus Interface

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3 C bus Interface The I C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips I C bus. Table 16.5 lists the I C bus interface Specifications, Figure 16.22 shows a Block Diagram of I C bus interface, and Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA.
  • Page 218 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Transfer clock generation circuit Output ICCR1 register control Transmit/receive ICCR2 register control circuit Noise ICMR register canceller ICDRT register SAR register Output control ICDRS register Noise Address comparison canceller circuit ICDRR register Bus state judgment circuit Arbitration judgment...
  • Page 219 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface SCL input SCL output SDA input SDA output (Master) SCL input SCL input SCL output SCL output SDA input SDA input SDA output SDA output (Slave2) (Slave1) Figure 16.23 External Circuit Connection Example of Pins SCL and SDA Rev.1.30 Dec 08, 2006 Page 201 of 315...
  • Page 220 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface IIC bus Control Register 1 b7 b6 b5 b4 b3 b2 Symbol Address After Reset 00B8h ICCR1 Bit Symbol Bit Name Function b3 b2 b1 b0 Transmit clock select bits 3 to 0 0 0 0 : f1/28 CKS0 0 0 0 1 : f1/40...
  • Page 221 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface IIC bus Control Register 2 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00B9h 01111101b ICCR2 Bit Symbol Bit Name Function — Nothing is assigned. If necessary, set to 0. —...
  • Page 222 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface IIC bus Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ICMR 00BAh 00011000b Bit Symbol Bit Name Function Bit counter 2 to 0 C bus format (remaining transfer bit count w hen read out and data bit count of next transfer w hen (1,2) w ritten.)
  • Page 223 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface IIC bus Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset 00BBh ICIER Bit Symbol Bit Name Function Transmit acknow ledge 0 : 0 is transmitted as acknow ledge bit in select bit receive mode.
  • Page 224 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface IIC bus Status Register b7 b6 b5 b4 b2 b1 Symbol Address After Reset 00BCh 0000X000b ICSR Bit Symbol Bit Name Function General call address When the general call address is detected , this flag (1,2) recognition flag is set to 1.
  • Page 225 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Slave Address Register b7 b6 b3 b2 Symbol Address Af ter Reset 00BDh Bit Symbol Bit Name Function Format select bit 0 : I C bus format 1 : Clock synchronous serial f ormat Slave address 6 to 0 Set an address dif f erent f rom that of the other SVA0...
  • Page 226 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface IIC bus Receive Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ICDRR 00BFh Function Store receive data When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR register and the next receive operation is enabled.

  • Page 227: Transfer Clock

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.1 Transfer Clock When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin.

  • Page 228: Interrupt Requests

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.2 Interrupt Requests The I C bus interface has six interrupt requests when the I C bus format is used and four when the clock synchronous serial format is used. Table 16.7 lists the Interrupt Requests of I C bus Interface.

  • Page 229: C Bus Interface Mode

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.3 C bus Interface Mode 16.3.3.1 C bus Format Setting the FS bit in the SAR register to 0 communicates in I C bus format. Figure 16.32 shows the I C bus Format and Bus Timing. The 1st frame following the start condition consists of 8 bits.
  • Page 230 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.3.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 16.33 and 16.34 show the Operating Timing in Master Transmit Mode (I C bus Interface Mode).
  • Page 231 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface (master output) (master output) Slave address (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRT register Address + R/W Data 1 Data 2 Address + R/W Data 1 ICDRS register (5) Data write to ICDRT Processing...
  • Page 232 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figures 16.35 and 16.36 show the Operating Timing in Master Receive Mode (I C bus Interface Mode).
  • Page 233 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Master transmit mode Master receive mode (master output) (master output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register RDRF bit in ICSR register ICDRS register Data 1 ICDRR register...
  • Page 234 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface (master output) (master output) (slave output) RDRF bit in ICSR register RCVD bit in ICCR1 register Data n-1 ICDRS register Data n Data n-1 Data n ICDRR register (6) Stop condition Processing (5) Set RCVD bit to 1 before (7) Read ICDRR register before...
  • Page 235 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.3.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal. Figures 16.37 and 16.38 show the Operating Timing in Slave Transmit Mode (I C bus Interface Mode).
  • Page 236 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Slave receive mode Slave transmit mode (master output) (master output) (slave output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register ICDRT register Data 1 Data 2 Data 3...
  • Page 237 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Slave receive mode Slave transmit mode (master output) (master output) (slave output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register Data n ICDRT register Data n ICDRS register...
  • Page 238 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.3.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 16.39 and 16.40 show the Operating Timing in Slave Receive Mode (I C bus Interface Mode).
  • Page 239 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface (master output) (master output) (slave output) (slave output) RDRF bit in ICSR register ICDRS register Data 1 Data 2 ICDRR register Data 1 Processing (2) Dummy read of ICDRR register (2) Read ICDRR register by program Figure 16.39 Operating Timing in Slave Receive Mode (I...

  • Page 240: Clock Synchronous Serial Mode

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.4 Clock Synchronous Serial Mode 16.3.4.1 Clock Synchronous Serial Format Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication. Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format. When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the MST bit is set to 0, the external clock is input.
  • Page 241 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.4.2 Transmit Operation In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
  • Page 242 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.4.3 Receive Operation In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).

  • Page 243: Noise Canceller

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.5 Noise Canceller The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure 16.44 shows a Block Diagram of Noise Canceller. The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal (or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit.

  • Page 244: Bit Synchronization Circuit

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.6 Bit Synchronization Circuit When setting the I C bus interface to master mode, the high-level period may become shorter in the following two cases: • If the SCL signal is driven L level by a slave device •...

  • Page 245: Examples Of Register Setting

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.7 Examples of Register Setting Figures 16.46 to 16.49 show Examples of Register Setting When Using I C bus interface. Start • Set the STOP bit in the ICSR register to 0. Initial setting •...
  • Page 246 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Master receive mode TEND bit ← 0 ICSR register (1) Set the TEND bit to 0 and set to master receive mode. (1,2) Set the TDRE bit to 0. TRS bit ← 0 ICCR1 register (2) Set the ACKBT bit to the transmit device.
  • Page 247 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Slave transmit mode (1) Set the AAS bit to 0. AAS bit ← 0 ICSR register (2) Set the transmit data (except the last byte). Write transmit data to ICDRT register (3) Wait until the ICRDT register is empty.
  • Page 248 R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface Slave receive mode (1) Set the AAS bit to 0. AAS bit ← 0 ICSR register (2) Set the ACKBT bit to the transmit device. ICIER register ACKBT bit ← 0 (3) Dummy read the ICDRR register Dummy read in ICDRR register (4) Wait until 1 byte is received.

  • Page 249: Notes On I 2 C Bus Interface

    R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface 16.3.8 Notes on I C bus Interface Set the IICSEL bit in the PMR register to 1 (select I C bus interface function) to use the I C bus interface. 16.3.8.1 Accessing of Registers Associated with I C bus Interface Wait for three instructions or more or four cycles or more after writing to the same register among the registers...

  • Page 250: 17. A/D Converter

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares pins P1_0 to P1_3. Therefore, when using these pins, ensure that the corresponding port direction bits are set to 0 (input mode).
  • Page 251 R8C/1A Group, R8C/1B Group 17. A/D Converter A/D conversion rate selection CKS0 = 1 fRING-fast CKS1 = 1 CKS0 = 0 φ AD CKS0 = 1 CKS1 = 0 CKS0 = 0 VCUT = 0 AVSS Resistor ladder VCUT = 1 VREF Successive conversion register ADCAP = 0...
  • Page 252 R8C/1A Group, R8C/1B Group 17. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ADCON0 00D6h 00000XXXb Bit Symbol Bit Name Function Analog input pin select b2 b1 b0 bits 1 0 0 : AN8 1 0 1 : AN9 1 1 0 : AN10 1 1 1 : AN11...
  • Page 253 R8C/1A Group, R8C/1B Group 17. A/D Converter A/D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ADCON2 00D4h Bit Symbol Bit Name Function A/D conversion method select bit 0 : Without sample and hold 1 : With sample and hold —...

  • Page 254: One-Shot Mode

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.1 One-Shot Mode In one-shot mode, the input voltage of one selected pin is A/D converted once. Table 17.2 lists the One-Shot Mode Specifications. Figure 17.4 shows Registers ADCON0 and ADCON1 in One-shot Mode. Table 17.2 One-Shot Mode Specifications Item...
  • Page 255 R8C/1A Group, R8C/1B Group 17. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset ADCON0 00D6h 00000XXXb Bit Symbol Bit Name Function Analog input pin select b2 b1 b0 bits 1 0 0 : AN8 1 0 1 : AN9 1 1 0 : AN10 1 1 1 : AN11...

  • Page 256: Repeat Mode

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.2 Repeat Mode In repeat mode, the input voltage of one selected pin is A/D converted repeatedly. Table 17.3 lists the Repeat Mode Specifications. Figure 17.5 shows Registers ADCON0 and ADCON1 in Repeat Mode. Table 17.3 Repeat Mode Specifications Item...
  • Page 257 R8C/1A Group, R8C/1B Group 17. A/D Converter A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 Symbol Address After Reset ADCON0 00D6h 00000XXXb Bit Symbol Bit Name Function Analog input pin select b2 b1 b0 bits 1 0 0 : AN8 1 0 1 : AN9 1 1 0 : AN10 1 1 1 : AN11...

  • Page 258: Sample And Hold

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.3 Sample and Hold When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate per pin increases to 28φAD cycles for 8-bit resolution or 33φAD cycles for 10-bit resolution. The sample and hold function is available in all operating modes.

  • Page 259: Internal Equivalent Circuit Of Analog Input Block

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.5 Internal Equivalent Circuit of Analog Input Block Figure 17.8 shows the Internal Equivalent Circuit of Analog Input Block. VCC VSS AVCC ON resistor approx. 0.6 k Ω Parasitic diode ON resistor approx. 2 k Ω Wiring resistor C = Approx.1.5 pF Analog input approx.

  • Page 260: Inflow Current Bypass Circuit

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.6 Inflow Current Bypass Circuit Figure 17.9 shows the Configuration of Inflow Current Bypass Circuit and Figure 17.10 shows an Example of Inflow Current Bypass Circuit where VCC or More is Applied. Fixed to GND level Unselected channel To the internal logic...

  • Page 261: Output Impedance Of Sensor Under A/D Conversion

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.7 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 17.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).

  • Page 262: Notes On A/D Converter

    R8C/1A Group, R8C/1B Group 17. A/D Converter 17.8 Notes on A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs). •...

  • Page 263: 18. Flash Memory

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18. Flash Memory 18.1 Overview In the flash memory, rewrite operations to the flash memory can be performed in three modes; CPU rewrite, standard serial I/O, and parallel I/O. Table 18.1 lists the Flash Memory Performance (refer to Table 1.1 Functions and Specifications for R8C/1A Group and Table 1.2 Functions and Specifications for R8C/1B Group for items not listed in Table 18.1).
  • Page 264 R8C/1A Group, R8C/1B Group 18. Flash Memory Table 18.2 Flash Memory Rewrite Modes Flash Memory CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode Function User ROM area is rewritten by User ROM area is rewritten User ROM area is executing software commands by a dedicated serial rewritten by a...

  • Page 265: Memory Map

    FMR1 register to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode). 2. This area is for storing the boot program provided by Renesas Technology. Figure 18.1 Flash Memory Block Diagram for R8C/1A Group Rev.1.30...
  • Page 266 FMR1 register to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode). 2. This area is for storing the boot program provided by Renesas Technology. Figure 18.2 Flash Memory Block Diagram for R8C/1B Group Rev.1.30...

  • Page 267: Functions To Prevent Rewriting Of Flash Memory

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.3 Functions to Prevent Rewriting of Flash Memory Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily. 18.3.1 ID Code Check Function This function is used in standard serial I/O mode.

  • Page 268: Rom Code Protect Function

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.3.2 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the OFS register in parallel I/O mode. Figure 18.4 shows the OFS Register. The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit.

  • Page 269: Cpu Rewrite Mode

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer.

  • Page 270: Ew0 Mode

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.1 EW0 Mode The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to 0, EW0 mode is selected.
  • Page 271 R8C/1A Group, R8C/1B Group 18. Flash Memory Figure 18.5 shows the FMR0 Register. Figure 18.7 shows the FMR4 Register. 18.4.2.1 FMR00 Bit This bit indicates the operating status of the flash memory. The bits value is 0 during programming, or erasure (suspend term included);...
  • Page 272 R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.2.10 FMR40 Bit The suspend function is enabled by setting the FMR40 bit to 1 (enable). 18.4.2.11 FMR41 Bit In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41 bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters erase-suspend mode.
  • Page 273 R8C/1A Group, R8C/1B Group 18. Flash Memory Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B7h 00000001b FMR0 Bit Symbol Bit Name Function ____ 0 : Busy (w riting or erasing in progress) RY/BY status flag FMR00...
  • Page 274 R8C/1A Group, R8C/1B Group 18. Flash Memory Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B5h 1000000Xb FMR1 Bit Symbol Bit Name Function — Reserved bit When read, the content is undefined. (b0) (1, 2) EW1 mode select bit...
  • Page 275 R8C/1A Group, R8C/1B Group 18. Flash Memory Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 01B3h 01000000b FMR4 Bit Symbol Bit Name Function Erase-suspend function 0 : Disable FMR40 enable bit 1 : Enable Erase-suspend request bit 0 : Erase restart...
  • Page 276 R8C/1A Group, R8C/1B Group 18. Flash Memory Figure 18.8 shows the Timing of Suspend Operation. Erasure Erasure Programming Programming Programming Programming Erasure Erasure starts suspends starts suspends restarts ends restarts ends During erasure During erasure During programming During programming FMR00 bit in Remains 0 during suspend FMR0 register FMR46 bit in...
  • Page 277 R8C/1A Group, R8C/1B Group 18. Flash Memory Figure 18.9 shows How to Set and Exit EW0 Mode. Figure 18.10 shows How to Set and Exit EW1 Mode. EW0 Mode Operating Procedure Rewrite control program Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled) Set registers CM0 and CM1 Execute software commands...
  • Page 278 R8C/1A Group, R8C/1B Group 18. Flash Memory On-chip oscillator mode (main clock stops) program Transfer an on-chip oscillator mode (main clock stops) Write 0 to the FMR01 bit before writing program to an area other than the flash memory. (CPU rewrite mode enabled) Write 1 to the FMSTP bit (flash memory stops.

  • Page 279: Software Commands

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.3 Software Commands The software commands are described below. Read or write commands and data in 8-bit units. Table 18.4 Software Commands First Bus Cycle Second Bus Cycle Command Data Data Mode Address Mode Address (D7 to D0)
  • Page 280 R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.3.4 Program Command The program command writes data to the flash memory in 1-byte units. By writing 40h in the first bus cycle and data to the write address in the second bus cycle, an auto-program operation (data program and verify) will start.
  • Page 281 R8C/1A Group, R8C/1B Group 18. Flash Memory (1, 2) Maskable interrupt EW0 Mode Start I = 1 (enable interrupt) FMR44 = 1 ? FMR40 = 1 FMR46 = 0 ? Write the command code 40h FMR42 = 1 Write data to the write address FMR46 = 1 ? Access flash memory FMR44 = 0 ?
  • Page 282 R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.3.5 Block Erase When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus cycle, an auto-erase operation (erase and verify) of the specified block starts. The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
  • Page 283 R8C/1A Group, R8C/1B Group 18. Flash Memory EW0 Mode (1, 2) Start Maskable interrupt I = 1 (enable interrupt) FMR43 = 1 ? FMR40 = 1 FMR46 = 0 ? Write the command code 20h FMR41 = 1 Write D0h to any block address FMR46 = 1 ? Access flash memory...

  • Page 284: Status Register

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.4 Status Register The status register indicates the operating status of the flash memory and whether an erase or program operation has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and FMR07 in the FMR0 register.

  • Page 285: Full Status Check

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.4.5 Full Status Check When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an error. Therefore, checking these status bits (full status check) can be used to determine the execution result. Table 18.6 lists the Errors and FMR0 Register Status.
  • Page 286 R8C/1A Group, R8C/1B Group 18. Flash Memory Command sequence error Full status check Execute the clear status register command (set these status flags to 0) FMR06 = 1 Command sequence error FMR07 = 1? Check if command is properly input Re-execute the command Erase error FMR07 = 1?

  • Page 287: Standard Serial I/O Mode

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a serial programmer which is suitable for the MCU. Standard serial I/O mode is used to connect with a serial programmer using a special clock asynchronous serial I/O.
  • Page 288 R8C/1A Group, R8C/1B Group 18. Flash Memory Table 18.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) Name Description VCC,VSS Power input Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. Reset input Reset input pin.
  • Page 289 R8C/1A Group, R8C/1B Group 18. Flash Memory RESET Connect oscillator circuit MODE Package: PLSP0020JB-A NOTE: 1. It is not necessary to connect an oscillating circuit when operating with the on-chip oscillator clock. Mode Setting Signal Value Voltage from programmer MODE VSS →...
  • Page 290 R8C/1A Group, R8C/1B Group 18. Flash Memory 18.5.1.1 Example of Circuit Application in Standard Serial I/O Mode Figure 18.18 shows an example of Pin Processing in Standard Serial I/O Mode 2, and Figure 18.19 shows Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer for details.

  • Page 291: Parallel I/O Mode

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.6 Parallel I/O Mode Parallel I/O mode is used to input and output software commands, addresses, and data necessary to control (read, program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel programmer for details on how to use it.

  • Page 292: Notes On Flash Memory

    R8C/1A Group, R8C/1B Group 18. Flash Memory 18.7 Notes on Flash Memory 18.7.1 CPU Rewrite Mode 18.7.1.1 Operating Speed Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode. 18.7.1.2 Prohibited Instructions The following instructions cannot be used in EW0 mode because they reference data in the flash memory:...
  • Page 293 R8C/1A Group, R8C/1B Group 18. Flash Memory Table 18.10 EW1 Mode Interrupts When Watchdog Timer, Oscillation When Maskable Interrupt Request Mode Status Stop Detection and Voltage Monitor 2 is Acknowledged Interrupt Request is Acknowledged EW1 During auto-erasure Auto-erasure is suspended after Once an interrupt request is (erase- suspend td(SR-SUS) and interrupt handling...

  • Page 294: 19. Electrical Characteristics

    R8C/1A Group, R8C/1B Group 19. Electrical Characteristics 19. Electrical Characteristics Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20°C to 105°C ). Table 19.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value...
  • Page 295 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.3 A/D Converter Characteristics Standard Symbol Parameter Conditions Unit Min. Typ. Max. − − − Resolution Bits − φ − − Absolute 10-bit mode = 10 MHz, V = 5.0 V ±3 accuracy φ...
  • Page 296 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support representative.
  • Page 297 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support representative.
  • Page 298 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Clock- Fixed time (97 µs) dependent time Access restart d(SR-SUS) Figure 19.2 Transition Time to Suspend Table 19.6 Voltage Detection 1 Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min.
  • Page 299 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset) Symbol Parameter Condition Standard Unit Min. Typ. Max. -20 ° C ≤ Topr ≤ 85 ° C − − Power-on reset valid voltage por2 det1 -20 °...
  • Page 300 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min. Typ. Max. − = 25 ° C − − High-speed on-chip oscillator frequency when the = 5.0 V, T reset is deasserted −...
  • Page 301 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.12 Timing Requirements of Clock Synchronous Serial I/O with Chip Select Standard Symbol Parameter Conditions Unit Min. Typ. Max. − − SSCK clock cycle time SUCYC − SSCK clock “H” width SUCYC −...
  • Page 302 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 or V SCS (output) or V FALL RISE SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SUCYC SSO (output) SSI (input) 4-Wire Bus Communication Mode, Master, CPHS = 0 or V SCS (output) or V...
  • Page 303 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 or V SCS (input) or V FALL RISE LEAD SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SUCYC SSO (input) SSI (output) 4-Wire Bus Communication Mode, Slave, CPHS = 0 or V SCS (input) or V...
  • Page 304 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics or V SSCK or V SUCYC SSO (output) SSI (input) Figure 19.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.1.30 Dec 08, 2006 Page 286 of 315 REJ09B0252-0130...
  • Page 305 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.13 Timing Requirements of I C bus Interface Standard Symbol Parameter Condition Unit Min. Typ. Max. − − SCL input cycle time +600 − − SCL input “H” width +300 SCLH − −...
  • Page 306 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.14 Electrical Characteristics (1) [V = 5 V] Standard Symbol Parameter Condition Unit Min. Typ. Max. − 2.0 − Output “H” voltage Except X = -5 mA = -200 µ A − 0.3 −...
  • Page 307 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85 °C, unless otherwise specified.) Table 19.15 Standard Symbol Parameter Condition Unit Min. Typ. Max. − Power supply current High-speed XIN = 20 MHz (square wave) = 3.3 to 5.5 V) mode High-speed on-chip oscillator off...
  • Page 308 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Timing Requirements = 0 V at Ta = 25 °C) [ V (Unless otherwise specified: V = 5 V, V = 5 V ] Table 19.16 XIN Input Standard Symbol Parameter Unit Min. Max.
  • Page 309 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.19 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLKi input cycle time c(CK) − CLKi input “H” width W(CKH) − CLKi input “L” width W(CKL) − TXDi output delay time d(C-Q) −...
  • Page 310 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.21 Electrical Characteristics (3) [V = 3V] Standard Symbol Parameter Condition Unit Min. Typ. Max. − 0.5 − Output “H” voltage Except X = -1 mA − 0.5 − Drive capacity = -0.1 mA HIGH = -50 µ...
  • Page 311 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85 °C, unless otherwise specified.) Table 19.22 Standard Symbol Parameter Condition Unit Min. Typ. Max. − Power supply current High-speed XIN = 20 MHz (square wave) = 2.7 to 3.3 V) mode High-speed on-chip oscillator off...
  • Page 312 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics = 0 V at Ta = 25 °C) [V Timing requirements (Unless Otherwise Specified: V = 3 V, V = 3 V] Table 19.23 XIN Input Standard Symbol Parameter Unit Min. Max. − XIN input cycle time c(XIN) −...
  • Page 313 R8C/1A Group, R8C/1B Group 19. Electrical Characteristics Table 19.26 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLKi input cycle time c(CK) − CLKi input “H” width W(CKH) − CLKi input “L” width W(CKL) − TXDi output delay time d(C-Q) −...

  • Page 314: 20. Usage Notes

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20. Usage Notes 20.1 Notes on Clock Generation Circuit 20.1.1 Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops.

  • Page 315: Notes On Interrupts

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.2 Notes on Interrupts 20.2.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0.

  • Page 316: Changing Interrupt Sources

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.2.5 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing.

  • Page 317: Changing Interrupt Control Register Contents

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.2.6 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents.

  • Page 318: Precautions On Timers

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.3 Precautions on Timers 20.3.1 Notes on Timer X • Timer X stops counting after a reset. Set the values in the timer and prescaler before the count starts. • Even if the prescaler and timer are read out in 16-bit units, these registers are read 1 byte at a time by the MCU.

  • Page 319: Notes On Timer C

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.3.3 Notes on Timer C Access registers TC, TM0, and TM1 in 16-bit units. The TC register can be read in 16-bit units. This prevents the timer value from being updated between when the low-order bytes and high-order bytes are being read.

  • Page 320: Notes On Serial Interface

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.4 Notes on Serial Interface • When reading data from the U0RB register either in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the U0RB register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0.

  • Page 321: Precautions On Clock Synchronous Serial Interface

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.5 Precautions on Clock Synchronous Serial Interface 20.5.1 Notes on Clock Synchronous Serial I/O with Chip Select Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select function.

  • Page 322: Notes On I 2 C Bus Interface

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.5.2 Notes on I C bus Interface Set the IICSEL bit in the PMR register to 1 (select I C bus interface function) to use the I C bus interface. 20.5.2.1 Accessing of Registers Associated with I C bus Interface Wait for three instructions or more or four cycles or more after writing to the same register among the registers associated with the I...

  • Page 323: Notes On A/D Converter

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.6 Notes on A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs). •...

  • Page 324: Notes On Flash Memory

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.7 Notes on Flash Memory 20.7.1 CPU Rewrite Mode 20.7.1.1 Operating Speed Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode. 20.7.1.2 Prohibited Instructions The following instructions cannot be used in EW0 mode because they reference data in the flash memory:...
  • Page 325 R8C/1A Group, R8C/1B Group 20. Usage Notes Table 20.2 EW1 Mode Interrupts When Watchdog Timer, Oscillation When Maskable Interrupt Request Mode Status Stop Detection and Voltage Monitor 2 is Acknowledged Interrupt Request is Acknowledged EW1 During auto-erasure Auto-erasure is suspended after Once an interrupt request is (erase- suspend td(SR-SUS) and interrupt handling...

  • Page 326: Notes On Noise

    R8C/1A Group, R8C/1B Group 20. Usage Notes 20.8 Notes on Noise 20.8.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-Up Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest wire possible. 20.8.2 Countermeasures against Noise Error of Port Control Registers During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the...

  • Page 327: 21. Notes On On-Chip Debugger

    R8C/1A Group, R8C/1B Group 21. Notes on On-Chip Debugger 21. Notes on On-Chip Debugger When using on-chip debugger to develop and debug programs for the R8C/1A Group and R8C/1B Group, take note of the following. Do not access the related UART1 registers. Some of the user flash memory and RAM areas are used by the on-ship debugger.

  • Page 328: Appendix 1. Package Dimensions

    R8C/1A Group, R8C/1B Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LSSOP20-4.4x6.5-0.65...
  • Page 329 R8C/1A Group, R8C/1B Group Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-HWQFN28-5x5-0.50 PWQN0028KA-B 28PJW-B 0.05g NOTE) DIMENSIONS " 1" AND " 2" DO NOT INCLUDE MOLD FLASH. Dimension in Millimeters Reference Symbol Min Nom Max 0.75...

  • Page 330: Appendix 2. Connection Examples Between Serial Writer And On-Chip Debugging Emulator

    R8C/1A Group, R8C/1B GroupAppendix 2. Connection Examples between Serial Writer and On-Chip Debugging Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows a Connection Example with E8 Emulator (R0E000080KCE00).

  • Page 331: Appendix 3. Example Of Oscillation Evaluation Circuit

    R8C/1A Group, R8C/1B Group Appendix 3. Example of Oscillation Evaluation Circuit Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit. RESET Connect oscillation circuit NOTE: 1. Write a program to perform the evaluation. Appendix Figure 3.1 Example of Oscillation Evaluation Circuit Rev.1.30...

  • Page 332: Register Index

    R8C/1A Group, R8C/1B Group Register Index Register Index AD ............235 KIEN ............97 ADCON0 ..........234 KUPIC ............83 ADCON1 ..........234 ADCON2 ..........235 ADIC ............83 AIER ............99 OCD ............62 OFS ..........104, 250 CM0 ............60 CM1 ............61 P1 .............29 CMP0IC ...........
  • Page 333 R8C/1A Group, R8C/1B Group Register Index TC ............143 TCC0 ............144 TCC1 ............145 TCIC ............83 TCOUT ........... 146 TCSS ..........111, 127 TM0 ............143 TM1 ............143 TX ............111 TXIC ............83 TXMR ............. 110 TZIC ............
  • Page 334 REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual R8C/1A Group, R8C/1B Group Hardware Manual REVISION HISTORY Description Rev. Date Page Summary − 0.10 Jun 30, 2005 First Edition issued 1.00 Sep 09, 2005 all pages “Under development” deleted Table 1.2 Performance Outline of the R8C/1B Group; Flash Memory: (Data area) →...
  • Page 335 REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual Description Rev. Date Page Summary 1.00 Sep 09, 2005 Table 5.18 Unassigned Pin Handling, Figure 5.11 Unassigned Pin Handling; “Port P4_2, P4_6, P4_7” → “Port P4_6, P4_7” “VREF” → “Port P4_2/VREF” revised Table 9.2 Bus Cycles for Access Space of the R8C/1B Group added, Table 9.3 Access Unit and Bus Operation;...
  • Page 336 REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual Description Rev. Date Page Summary 1.00 Sep 09, 2005 Figure 16.46 Example of Register Setting in Master Transmit Mode (Clock Synchronous Serial Mode); ‘ “ • Set the IICSEL bit in the PMR register to “1” ’ added Table 17.1 Performance of A/D Converter •...
  • Page 337 REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual Description Rev. Date Page Summary − 1.10 Mar 17, 2006 Products of PWQN0028KA-B package included “or SDIP” → “SDIP or a 28-pin plastic molded-HWQFN” 2, 3 Table 1.1, Table 1.2; “28-pin molded-plastic HWQFN” added 5, 6 Table 1.3, Table 1.4;...
  • Page 338 REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual Description Rev. Date Page Summary = 2.2 to → 2.7 to 1.10 Mar 17, 2006 Table 19.13; NOTE: 1. V 286, 290 Table 19.15, Table 19.22; The title revised, Condition of Stop Mode “Topr = 25 °C”...
  • Page 339 REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual Description Rev. Date Page Summary 1.30 Dec 08, 2006 Figure 10.8 added Figure 10.9 added 10.6.1 revised 10.6.2 “Program example to execute the WAIT instruction” revised Table 12.6 revised Figure 13.2; WDC After Reset “00011111b” → “00X11111b” Figure 15.7 revised Figure 15.10 revised 15.3 “To check receive errors, read the UiRB register and then use the...
  • Page 340 R8C/1A Group, R8C/1B Group Hardware Manual Publication Date : Rev.0.10 Jun 30, 2005 Rev.1.30 Dec 08, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan...
  • Page 341 R8C/1A Group, R8C/1B Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0252-0130...

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