Interrupts And Interrupt Vectors - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
12.1.5

Interrupts and Interrupt Vectors

There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt
vector. When an interrupt request is acknowledged, the CPU branches to the address set in the
corresponding interrupt vector. Figure 12.2 shows an Interrupt Vector.
Vector address (L)
Vector address (H)
Figure 12.2 Interrupt Vector
12.1.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 12.1 lists the Fixed Vector
Tables. The vector addresses (H) of fixed vectors are used by the ID code check function. For
details, refer to 17.3 Functions to Prevent Rewriting of Flash Memory.
Table 12.1 Fixed Vector Tables
Interrupt Source
Undefined instruction
Overflow
BRK instruction
Address match
(1)
Single step
• Watchdog timer
• Oscillation stop
detection
• Voltage monitor 2
(1)
Address break
(Reserved)
Reset
NOTE:
1. Do not use these interrupts. They are for use by development tools only.
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
MSB
0 0 0 0
0 0 0 0
Vector Addresses
Address (L) to (H)
0FFDCh to 0FFDFh
0FFE0h to 0FFE3h
0FFE4h to 0FFE7h
0FFE8h to 0FFEBh
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
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Low address
Mid address
High address
0 0 0 0
Remarks
Interrupt on UND
instruction
Interrupt on INTO
instruction
If the content of address
0FFE7h is FFh, program
execution starts from the
address shown by the
vector in the relocatable
vector table.
12. Interrupts
LSB
Reference
R8C/Tiny Series Software
Manual
12.4 Address Match
Interrupt
• 13. Watchdog Timer
• 10. Clock Generation
Circuit
• 7. Voltage Detection
Circuit
5. Resets