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R8C/18 Group, R8C/19 Group
14.1.2
Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with inverted
polarity is output from the CNTR0 pin each time the timer underflows (refer to Table 14.3 Pulse
Output Mode Specifications). Figure 14.5 shows the TXMR Register in Pulse Output Mode.
Table 14.3
Pulse Output Mode Specifications
Item
Count sources
Count operations
Divided ratio
Count start condition
Count stop condition
Interrupt request
generation timing
INT10/CNTR00
pin function
CNTR0 pin function
Read from timer
Write to timer
Select functions
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TX register is
written to.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
f1, f2, f8, fRING
• Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1/(n+1)(m+1) n: value set in PREX register, m: value set in TX register
1 (count starts) is written to the TXS bit in the TXMR register.
0 (count stops) is written to the TXS bit in the TXMR register.
When timer X underflows [timer X interrupt].
Pulse output
Programmable I/O port, or inverted output of CNTR0
The count value can be read out by reading registers TX and PREX.
• When registers TX and PREX are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TX and PREX are written during the count, the value is written
to each reload register of registers TX and PREX at the following count source
input, the data is transferred to the counter at the second count source input,
and the count re-starts at the third count source input.
• INT1/CNTR0 signal polarity switch function
The R0EDG bit can select the polarity level when the pulse output starts.
• Inverted pulse output function
The pulse which inverts the polarity of the CNTR0 output can be output from
the CNTR0 pin (selected by TXOCNT bit).
Page 107 of 233
Specification
14. Timers
(1)
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