Count Source Protection Mode Disabled - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
13.1

Count Source Protection Mode Disabled

The count source of the watchdog timer is the CPU clock when count source protection mode is
disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode
Disabled).
Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Item
Count source
Count operation
Period
Count start conditions
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow • When the PM12 bit in the PM1 register is set to 0.
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
CPU clock
Decrement
Division ratio of prescaler (n) × count value of watchdog timer (32768)
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
divides by 16, the period is approximately 32.8 ms.
The WDTON bit
the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset).
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting).
The watchdog timer and prescaler start counting automatically after
reset.
• Reset
• Write 00h to the WDTR register before writing FFh.
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1.
Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.)
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Specification
CPU clock
(2)
in the OFS register (0FFFFh) selects the operation of
13. Watchdog Timer
(1)