Cntr0 Pin Select Function - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
UiC1 register 1
RE bit 0
RXDi
Transfer clock
UiC1 register
1
RI bit
0
SiRIC register
1
IR bit
0
The above timing diagram applies when the register bits are set as follows:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (1 stop bit)
i = 0 or 1
Figure 15.11 Receive Timing in UART Mode
15.2.1

CNTR0 Pin Select Function

The CNTRSEL bit in the UCON register selects whether P1_7 is used as the CNTR00/INT10 input
pin or P1_5 is used as the CNTR01/INT11 input pin.
When the CNTRSEL bit is set to 0, P1_7 is used as the CNTR00/INT10 pin and when the CNTRSEL
bit is set to 1, P1_5 is used as the CNTR01/INT11 pin.
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Start bit
Determined to be "L" Receive data taken in
Reception triggered when transfer clock
is generated by falling edge of start bit
Page 160 of 233
D0 D1
Transferred from UARTi receive
register to UiRB register
Set to 0 when interrupt request is accepted, or set by a program
15. Serial Interface
Stop bit
D7