Renesas R8C/18 Series Hardware Manual page 38

R8C/18 Group, R8C/19 Group
Table 5.2 shows the Pin Functions after Reset, Figure 5.2 shows CPU Register Status after Reset and
Figure 5.3 shows Reset Sequence.
Table 5.2 Pin Functions after Reset
Pin Name
P1
P3_3 to P3_5, P3_7
P4_2, P4_5 P4_7
to
b15
Figure 5.2 CPU Register Status after Reset
fRING-S
Internal reset
signal
CPU clock
Address
(internal address
signal)
NOTE:
1. Hardware reset
Figure 5.3 Reset Sequence
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Input port
Input port
Input port
b15
0000h
0000h
0000h
0000h
0000h
0000h
0000h
b19
00000h
Content of addresses 0FFFEh to 0FFFCh
b15
0000h
0000h
0000h
b15
0000h
b8
b7
IPL
U I
(1)
20 cycles or more needed
Flash memory activation
(CPU clock × 11 cycles)
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Pin Functions
b0
Data register (R0)
Data register (R1)
Data register (R2)
Data register (R3)
Address register (A0)
Address register (A1)
Frame base register (FB)
b0
Interrupt table register (INTB)
Program counter (PC)
b0
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
b0
Flag register (FLG)
b0
O B S Z D C
CPU clock × 28 cycles
0FFFCh 0FFFEh
0FFFDh Content of reset vector
5. Resets