Int Interrupt; Int0 Interrupt - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
12.2

INT Interrupt

12.2.1

INT0 Interrupt

The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in
the INTEN register is set to 1 (enable). The edge polarity is selected using the INT0PL bit in the
INTEN register and the POL bit in the INT0IC register.
Inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the external trigger input pin of timer Z.
Figure 12.11 shows Registers INTEN and INT0F.
External Input Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
NOTES:
1. Set the INT0EN bit w hile the INOSTG bit in the PUM register is set to 0 (one-shot trigger disabled).
2. When setting the INT0PL bit to 1 (both edges), set the POL bit in the INT0IC register to 0 (selects falling edge).
3. The IR bit in the INT0IC register may be set to 1 (requests interrupt) w hen the INT0PL bit is rew ritten. Refer to 12.5.5
Changing Interrupt Sources.
______
INT0 Input Filter Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Figure 12.11 Registers INTEN and INT0F
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
0096h
INTEN
Bit Symbol Bit Name
_____
INT0 input enable bit
INT0EN
_____
INT0 input polarity select bit
INT0PL
— Reserved bits
(b7-b2)
Symbol Address
001Eh
INT0F
Bit Symbol Bit Name
_____
INT0 input filter select bits
INT0F0
INT0F1
— Reserved bit
(b2)
— Nothing is assigned. If necessary, set to 0.
(b7-b3) When read, the content is 0.
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(1) 0 : Disable
1 : Enable
(2, 3) 0 : One edge
1 : Both edges
Set to 0.
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0.
12. Interrupts
After Reset
00h
Function
After Reset
00h
Function
RW
RW
RW
RW
RW
RW
RW
RW
—