Renesas R8C/18 Series Hardware Manual page 94

R8C/18 Group, R8C/19 Group
12.1.6.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable
interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the
IR bit is set to 0 (= interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
12.1.6.3 Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority
Levels Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
• I flag = 1
•
IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0 and IPL are independent of each other. They do not affect one
another.
Table 12.3 Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 Bits Interrupt Priority Level
000b Level 0 (interrupt disabled)
001b Level 1
010b Level 2
011b Level 3
100b Level 4
101b Level 5
110b Level 6
111b Level 7
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Priority Order
−
Low
High
Page 79 of 233
Table 12.4 Interrupt Priority Levels Enabled by
IPL
IPL Enabled Interrupt Priority Levels
000b Interrupt level 1 and above
001b Interrupt level 2 and above
010b Interrupt level 3 and above
011b Interrupt level 4 and above
100b Interrupt level 5 and above
101b Interrupt level 6 and above
110b Interrupt level 7 and above
111b All maskable interrupts are disabled
12. Interrupts