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R8C/18 Group, R8C/19 Group
CM10 = 1 (stop mode)
RESET
Power-on reset
Software reset
Interrupt request
WAIT
instruction
XIN
CM05
CM02, CM05, CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
HRA00, HRA01: Bits in HRA0 register
Oscillation Stop Detection Circuit
Main clock
NOTE:
Figure 10.1
Clock Generation Circuit
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
HRA1 register
Frequency adjustable
High-speed
HRA00
on-chip
oscillator
Low-speed
on-chip
CM14
oscillator
S Q
R
Oscillation
stop
S Q
detection
Main clock
R
CM13
XOUT
CM13
CM02
a
Forcible discharge when OCD0
Pulse generation
circuit for clock
Charge,
edge detection and
discharge
charge, discharge
circuit
control circuit
OCD1
1. Set the same value in bits OCD1 and OCD0.
Page 54 of 233
HRA2 register
On-chip oscillator clock
fRING-fast
fRING128
fRING
HRA01 = 1
1/128
HRA01 = 0
Power-on
reset circuit
fRING-S
Voltage
detection
circuit
b
c
d
e
OCD2 = 1
a
Divider
OCD2 = 0
System clock
d
b
c
1/2
1/2
1/2
CM06 = 0
CM17 to CM16 = 10b
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
(1)
= 0
Oscillation stop detection
interrupt generation
circuit detection
(1)
Watchdog
timer interrupt
Voltage monitor
2 interrupt
OCD2 bit switch signal
CM14 bit switch signal
10. Clock Generation Circuit
Watchdog
timer
INT0
Timer C
Timer X
Timer Z
f1
f2
f4
f8
g
f32
h
CPU clock
g
e
1/2
1/2
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
h
Detail of divider
Oscillation stop detection,
Watchdog timer,
Voltage monitor 2 interrupt
UART1
Comparator
UART0
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