Interrupt Control - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
12.1.6

Interrupt Control

The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to
enable or disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in
each interrupt control register.
Figure 12.3 shows the Interrupt Control Register and Figure 12.4 shows the INT0IC Register
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.5.6 Changing Interrupt Control Register Contents.
Figure 12.3 Interrupt Control Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
(2)
Symbol
KUPIC
ADIC
CMP1IC
S0TIC, S1TIC
S0RIC, S1RIC
TXIC
TZIC
INT1IC
INT3IC
TCIC
CMP0IC
Bit Symbol Bit Name
Interrupt priority level select bits
ILVL0
ILVL1
ILVL2
Interrupt request bit
IR
— Nothing is assigned. If necessary, set to 0.
(b7-b4) When read, the content is undefined.
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Address
004Dh
004Eh
0050h
0051h, 0053h
0052h, 0054h
0056h
0058h
0059h
005Ah
005Bh
005Ch
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
12. Interrupts
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Function
RW
RW
RW
RW
RW
(1)
—