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R8C/18 Group, R8C/19 Group
A/D Control Register 0
b7 b6 b5 b4
b3 b2
b1
b0
1
1
1
NOTES:
1.
If the ADCON0 register is rew ritten during comparator conversion, the conversion result is undefined.
2.
Bits CH0 to CH2 are enabled w hen the ADGSEL0 bit is set to 1. After setting the ADGSEL0 bit to 1, w rite to bits CH0
to CH2.
3.
When changing comparator conversion operating mode, set the analog input pin again.
4.
Set the øAD frequency to 10 MHz or below .
5.
To use the comparator, set the ADGSEL0 bit to 1.
A/D Control Register 1
b7 b6 b5 b4
b3 b2 b1 b0
0 0 0
0
0
0
0
NOTE:
1.
If the ADCON1 register is rew ritten during comparator conversion, the conversion result is undefined.
Figure 16.5
Registers ADCON0 and ADCON1 in Repeat Mode
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
(1)
Symbol
Address
ADCON0
00D6h
Bit Symbol
Bit Name
Analog input pin select
CH0
(2)
bits
CH1
CH2
Comparator conversion
MD
operating mode select bit
Analog input group select
ADGSEL0
(5)
bit
Comparator conversion
ADCAP
automatic start bit
Comparator conversion
ADST
start flag
Frequency select bit 0
CKS0
(1)
Symbol
Address
00D7h
ADCON1
Bit Symbol
Bit Name
—
Reserved bits
(b3-b0)
Frequency select bit 1
CKS1
—
Reserved bits
(b7-b5)
Page 170 of 233
After Reset
00000XXXb
Function
b2 b1 b0
1 0 0 : AN8
1 0 1 : AN9
1 1 0 : AN10
1 1 1 : AN11
Other than above : Do not set.
1 : Repeat mode
(3)
0 : Disabled
1 : Enabled (AN8 to AN11)
0 : Starts at softw are trigger (ADST bit).
1 : Starts at capture (requests timer Z interrupt).
0 : Disables comparator conversion.
1 : Starts comparator conversion.
[When CKS1 in ADCON1 register = 0]
0 : Selects f4.
1 : Selects f2.
[When CKS1 in ADCON1 register = 1]
(4)
0 : Selects f1.
1 : fRING-fast
After Reset
00h
Function
Set to 0.
Refer to the description of the CKS0 bit in the
ADCON0 register function.
Set to 0.
16. Comparator
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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