Table of Contents
Advertisement
R8C/18 Group, R8C/19 Group
1SP
RXDi
SP
2SP
SP
SP
Figure 15.2
UARTi Transmit/Receive Unit
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
PRYE = 0
Clock
PAR
synchronous
disabled
type
SP
PAR
PAR
UART
enabled
PRYE = 1
0
0
0
0
0
PRYE = 1
PAR
UART
2SP
enabled
PAR
1SP
Clock
PAR
synchronous
disabled
type
PRYE = 0
0
Page 147 of 233
Clock
synchronous
type
UART (7 bits)
UART (7 bits)
UART (8 bits)
Clock
UART (9 bits)
synchronous
type
UART (8 bits)
UART (9 bits)
0
0
D8
D7
Data bus high-order bits
Data bus low-order bits
D8
D7
UART (8 bits)
UART (9 bits)
Clock
synchronous
UART (9 bits)
type
UART (7 bits)
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
NOTE:
1.Clock synchronous type is implemented in UART0 only.
15. Serial Interface
UARTi receive register
D6
D5
D4
D3
D2
D1
D0
MSB/LSB conversion circuit
MSB/LSB conversion circuit
D6
D5
D4
D3
D2
D1
D0
UARTi transmit register
i = 0 or 1
SP: Stop bit
PAR: Parity bit
UiRB register
UiTB register
TXDi
Advertisement
Table of Contents
