Renesas R8C/18 Series Hardware Manual page 104

R8C/18 Group, R8C/19 Group
Timer C Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
When the same value from the INT3
2. When the TCC00 bit in the TCC0 register is set to 0 (count stops), rew rite the TCC13 bit.
3. When the TCC13 bit is set to 0 (input capture mode), set bits TCC12 and TCC14 to TCC17 to 0.
Figure 12.16 TCC1 Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
009Bh
TCC1
Bit Symbol Bit Name
_____
INT3 filter select bits
TCC10
TCC11
Timer C counter reload select
(2, 3)
bit
TCC12
Compare 0/capture select bit
TCC13
Compare 0 output mode select
(3)
bits
TCC14
TCC15
Compare 1 output mode select
(3)
bits
TCC16
TCC17
_____
pin is sampled three times continuously, the input is determined.
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(1)
b1b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
0 : No reload
1 : Set TC register to 0000h w hen compare 1
is matched.
0 : Capture select (input capture mode)
1 : Compare 0 output select
(output compare mode)
b5 b4
0 0 : CMP output remains unchanged even
w hen compare 0 is matched.
0 1 : CMP output is reversed w hen compare
0 signal is matched.
1 0 : CMP output is set to "L" w hen compare
0 signal is matched.
1 1 : CMP output is set to "H" w hen compare
0 signal is matched.
b7 b6
0 0 : CMP output remains unchanged even
w hen compare 1 is matched.
0 1 : CMP output is reversed w hen compare
1 signal is matched.
1 0 : CMP output is set to "L" w hen compare
1 signal is matched.
1 1 : CMP output is set to "H" w hen compare
1 signal is matched.
12. Interrupts
After Reset
00h
Function
(2)
RW
RW
RW
RW
RW
RW
RW
RW
RW