Renesas R8C/18 Series Hardware Manual page 62

R8C/18 Group, R8C/19 Group
Voltage monitor 1 reset
Vdet1
Sampling
timing
Internal reset signal
Operation when the VW1C1 bit in the VW1C register is set to 0 (digital filter enabled).
Voltage monitor 2 interrupt
Vdet2
Sampling
timing
VW2C2 bit in
VW2C register
Voltage monitor 2
interrupt request
Operation when the VW2C1 bit in the VW2C register is set to 0 (digital filter enabled)
and the VW2C6 bit is set to 0 (voltage monitor 2 interrupt mode).
Figure 7.7 Operating Example of Digital Filter
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
VCC
Sampling clock of digital filter x 4 cycles
VCC
Sampling clock of digital filter x 4 cycles
1
0
1
0
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Sampling clock of digital filter x 4 cycles
Set to 0 by a program
Set to 0 by an interrupt
request acknowledgment
7. Voltage Detection Circuit