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R8C/18 Group, R8C/19 Group
16. Comparator
The comparator compares the electric potential input from the VREF pin with analog input.
The analog input shares pins P1_0 to P1_3. Therefore, when using these pins, ensure the corresponding
port direction bits are set to 0 (input mode).
The result of comparator conversion is stored in the AD register.
Table 16.1 lists the Comparator Performance. Figure 16.1 shows a Comparator Block Diagram.
Figures 16.2 and 16.3 show the Associated Comparator Registers.
Table 16.1
Comparator Performance
Item
Comparator conversion
method
Analog input voltage
Operating clock φAD
Absolute accuracy
Operating mode
Analog input pin
Comparator conversion start
conditions
Conversion rate per pin
NOTE:
1. The φAD frequency must be 10 MHz or below.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
Comparator
0 V to AVCC
4.2 V ≤ AVCC ≤ 5.5 V fRING-fast, f1, f2, f4
(1)
2.7 V ≤ AVCC < 4.2 V f2, f4
AVCC = 2.7 to 5.5 V ± 20 mV
One-shot and repeat modes
4 pins (AN8 to AN11)
• Software trigger
Set the ADST bit in the ADCON0 register to 1 (comparator conversion
starts).
• Capture
A timer Z interrupt request is generated while the ADST bit is set to 1.
10φAD cycles
Page 163 of 233
Performance
16. Comparator
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