Renesas RA Series Quick Design Manual
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Renesas RA Family
RA4 Quick Design Guide
Introduction
This document answers common questions and points out subtleties of the MCU that might be missed
unless the hardware manual was extensively reviewed. The document is not intended to be a replacement
for the hardware manual; it is intended to supplement the manual by highlighting some key items most
engineers will need to start their own design. It also discusses some design decisions from an application
point of view.
Target Device
RA4 MCU Series
Contents
1.
Power Supplies ........................................................................................................................ 4
1.1
References .............................................................................................................................................. 4
2.
Emulator Support ..................................................................................................................... 5
2.1
SWD Interface ......................................................................................................................................... 6
2.2
JTAG Interface ........................................................................................................................................ 7
2.3
Serial Programming Interface using SCI ................................................................................................. 8
2.4
2.5
Multiple Emulator Interface .................................................................................................................... 10
2.6
Software Setups for Emulator Connections .......................................................................................... 11
2.6.1
SWD and JTAG Interfaces .................................................................................................................. 11
2.6.2
Trace Port ............................................................................................................................................ 11
3.
MCU Operating Modes .......................................................................................................... 12
4.
Option Setting Memory .......................................................................................................... 12
4.1
Option Setting Memory Registers ......................................................................................................... 15
5.
Clock Circuits ......................................................................................................................... 15
5.1
Reset Conditions ................................................................................................................................... 16
5.2
Clock Frequency Requirements ............................................................................................................ 16
5.2.1
Requirements for USB Communications ............................................................................................ 17
5.2.2
Requirements for Programming and Erasing ROM or Data Flash ...................................................... 17
5.3
Lowering Clock Generation Circuit (CGC) Power Consumption ........................................................... 17
5.4
Writing the System Clock Control Registers ......................................................................................... 17
5.5
Clock Setup Example ............................................................................................................................ 18
5.6
HOCO Accuracy .................................................................................................................................... 19
5.7
Flash Interface Clock ............................................................................................................................. 19
5.8
Board Design ......................................................................................................................................... 19
5.9
External Crystal Resonator selection .................................................................................................... 20
R01AN5988EU0100 Rev.1.00
Jul.21.21
Application Note
®
®
Support ................................ 9
Page 1 of 51
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Related Manuals for Renesas RA Series
Summary of Contents for Renesas RA Series
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Page 1: Table Of Contents
Application Note Renesas RA Family RA4 Quick Design Guide Introduction This document answers common questions and points out subtleties of the MCU that might be missed unless the hardware manual was extensively reviewed. The document is not intended to be a replacement for the hardware manual;... - Page 2 Renesas RA Family RA4 Quick Design Guide 5.10 External Clock Input ..........................20 Reset Requirements and the Reset Circuit ................21 Pin Reset ............................... 22 Power-On Reset ............................ 22 VBATT-Selected Voltage Power-On Reset ................... 22 Independent Watchdog Timer Reset ..................... 23 Watchdog Timer Reset ..........................
- Page 3 Renesas RA Family RA4 Quick Design Guide 10.7 Electrical Characteristics ........................41 11. Module Stop Function ......................41 12. Interrupt Control Unit ......................41 13. Low Power Consumption ....................... 43 14. Buses ............................ 46 14.1 Bus Error Monitoring..........................47 14.1.1 Bus Error Types........................... 47 14.1.2 Operations When a Bus Error Occurs ....................
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Page 4: Power Supplies
Renesas RA Family RA4 Quick Design Guide 1. Power Supplies The RA family has digital power supplies and analog power supplies. The power supplies use the following pins. Table 1. Digital Power Supplies Symbol Name Description Power supply Power supply pin. Connect to the system power supply. -
Page 5: Emulator Support
Renesas RA Family RA4 Quick Design Guide Chapter 5, “Resets”, discusses the Power-On Reset and how to differentiate this from other reset sources. Chapter 7, “Low Voltage Detection”, provides details on the Low-Voltage Detection Circuit that can be used to monitor the power supply. Chapter 6, “Option-Setting Memory”, additionally describes how to enable Low- Voltage Detection 0 Circuit automatically at startup. -
Page 6: Swd Interface
Renesas RA Family RA4 Quick Design Guide 2.1 SWD Interface The following diagram shows the typical connectivity of the debug interface when using Serial Wire Debug (SWD). Figure 1. SWD Interface Connections Note: 1. The output of the reset circuit of the user system must be open collector. -
Page 7: Jtag Interface
Renesas RA Family RA4 Quick Design Guide 2.2 JTAG Interface The following diagram shows the typical connectivity of the debug interface when using an ARM-standard JTAG debug interface. Figure 2. JTAG Interface Connections Note: 1. The output of the reset circuit of the user system must be open collector. -
Page 8: Serial Programming Interface Using Sci
Renesas RA Family RA4 Quick Design Guide 2.3 Serial Programming Interface using SCI The following diagram shows the typical connectivity of the serial programming interface using SCI. Figure 3. Serial Programming Interface using SCI Connections Note: 1. The output of the reset circuit of the user system must be open collector. -
Page 9: Serial Programming Interface Using Sci: Devices With Arm
Renesas RA Family RA4 Quick Design Guide ® ® 2.4 Serial Programming Interface using SCI: Devices with Arm TrustZone Support The following diagram shows the typical connectivity of the serial programming interface using SCI for devices that include TrustZone support. Note the additional connection of P201/MD, which enables the programming of the Arm TrustZone IDAU boundary register settings. -
Page 10: Multiple Emulator Interface
Renesas RA Family RA4 Quick Design Guide 2.5 Multiple Emulator Interface The following diagram shows the typical connectivity of the debug interface to support multiple emulator types, including SWD, JTAG, SCI Serial Programming, and TrustZone support. Figure 5. Multiple Emulator Interface Connections Notes: 1. -
Page 11: Software Setups For Emulator Connections
Trace ports can also be enabled at runtime by using the Pin Configurator in Renesas FSP, but some trace data may be lost in this case. Figure 6. Enabling Trace Ports at Runtime Using FSP Configurator R01AN5988EU0100 Rev.1.00... -
Page 12: Mcu Operating Modes
Renesas RA Family RA4 Quick Design Guide 3. MCU Operating Modes The RA4 MCU series can enter one of two modes after reset: Single-chip mode or SCI/USB boot mode. The boot mode is selected by the MD pin: Table 6. - Page 13 Renesas RA Family RA4 Quick Design Guide The registers are detailed in the “Option Setting Memory” chapter in the Hardware User’s Manual. The flash option registers occupy space in the code flash memory map. Although the registers are located in a portion of the flash memory that was reserved on the RA MCUs, it is possible that some customers may store data in these locations inadvertently.
- Page 14 Renesas RA Family RA4 Quick Design Guide Figure 9. Option Function Select Registers for RA4M3 R01AN5988EU0100 Rev.1.00 Page 14 of 51 Jul.21.21...
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Page 15: Option Setting Memory Registers
LVD0 enable after reset HOCO startup after reset Renesas FSP Configurator supports setting of option memory in BSP settings, as shown in the following figure for RA4M3 MCU. The settings made through the FSP configurator are reflected in the binary file compiled to operate on the MCU. -
Page 16: Reset Conditions
Renesas RA Family RA4 Quick Design Guide Table 7. RA4 Oscillators Oscillator Input Source Frequency Primary Uses Main clock External 8 MHz to 24 MHz PLL input, PLL2 input , main crystal/resonator system clock, CLKOUT, CAN clock, CAC clock, LCD clock -or- ... -
Page 17: Requirements For Usb Communications
Renesas RA Family RA4 Quick Design Guide Table 9. Frequency Range for Arm Cortex-M33 MCU Internal Clocks ICLK PCLKA PCLKB PCLKC PCLKD Maximum Frequency [MHz] Minimum Frequency [MHz] FCLK USBCLK CANCLK Maximum Frequency [MHz] Minimum Frequency [MHz] Note 1. -
Page 18: Clock Setup Example
Figure 11. Timing of Clock Source Switching 5.5 Clock Setup Example Renesas FSP provides a simple, visual clock configuration tool for RA4M3 MCU shown as follows. R01AN5988EU0100 Rev.1.00 Page 18 of 51 Jul.21.21... -
Page 19: Hoco Accuracy
Renesas RA Family RA4 Quick Design Guide Figure 12. Clock Settings Using Renesas FSP Configurator 5.6 HOCO Accuracy The internal high-speed on-chip oscillator (HOCO) runs at 16 MHz, 18 MHz, or 20 MHz for Arm Cortex-M33 core devices, and 24 MHz, 32 MHz, 48 MHz, or 64 MHz for Arm Cortex-M4 devices, with a typical accuracy of +/-2% or better. -
Page 20: External Crystal Resonator Selection
Renesas RA Family RA4 Quick Design Guide When a crystal resonator is used, place the resonator and its load capacitors as close to the MCU clock pins (XTAL/EXTAL, XCIN/XCOUT) as possible. Avoid routing any other signals between the crystal resonator and the MCU. -
Page 21: Reset Requirements And The Reset Circuit
Renesas RA Family RA4 Quick Design Guide Figure 15. Equivalent Circuit for External Clock Note: The frequency of the external clock input can only be changed when the main clock oscillator is stopped. Do not change the frequency of the external clock input when the setting of the Main Clock Oscillator Stop bit (MOSCCR.MOSTP) is 0. -
Page 22: Pin Reset
Renesas RA Family RA4 Quick Design Guide ® There are thirteen or fourteen types of resets for Arm Cortex-M33 devices, depending on the specific device. ® Table 12. Arm Cortex-M33 Device Resets Reset Name Source Pin reset RES# is driven low... -
Page 23: Independent Watchdog Timer Reset
Renesas RA Family RA4 Quick Design Guide 6.4 Independent Watchdog Timer Reset This is an internal reset generated by the Independent Watchdog Timer (IWDT). When the IWDT underflows, an independent watchdog timer reset is optionally generated (NMI can be generated instead) and the IWDTRF bit in RSTSR1 is set to a 1. After a short delay the IWDT reset is canceled. -
Page 24: Determining The Reset Source
“Determination of Reset Generation Source” for the flow diagram. The following sample code shows how to determine if a reset is caused by Software Reset, Deep Software Standby or Power-On Reset using CMSIS based register structure in Renesas FSP. /* Deep Software Standby Reset */ if(1 == R_SYSTEM->RSTSR0_b.DPSRSTF) - Page 25 Renesas RA Family RA4 Quick Design Guide Figure 16. Secure and Non-Secure Regions Note: All external memory accesses are considered to be Non-Secure. Code Flash and SRAM can be divided into Secure, Non-Secure, and Non-Secure Callable. All secure memory accesses from the Non-Secure region MUST go through the Non-Secure Callable gateway and target a specific Secure Gateway (SG) assembler instruction.
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Page 26: Emulator Support For Trustzone
• Arm TrustZone Security section in the relevant MCU Hardware User’s Manual. 7.2 Emulator Support for TrustZone Renesas provides an emulator which supports both debugging using SWD or JTAG communication and serial programming using SCI communication. This emulator makes it easy to switch between debugging and serial programming. - Page 27 Renesas RA Family RA4 Quick Design Guide Table 13. Pin Assignments for Emulator Pin No. JTAG Serial Programming Using SCI P108/SWDIO P108/SWDIO P300/SWCLK P300/TCK P201/MD Wired OR with P201/MD Wired OR with P201/MD P109/SWO/TXD9 P109/TDO/TXD9 P109/TDO/TXD9 P110/SWO/RXD9 P110/TDI/RXD9 P110/TDI/RXD9 GNDdetect...
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Page 28: Device Lifecycle Management
Renesas RA Family RA4 Quick Design Guide Figure 19. Emulator Connections for MCUs that Support Trustzone 7.2.1 Device Lifecycle Management RA4 MCUs with Arm Cortex-M33 cores are equipped with Device Lifecycle Management (DLM), which is the management of the process by which a product goes from inception to development to production and then eventually end-of-life. -
Page 29: Memory
Renesas RA Family RA4 Quick Design Guide 8. Memory The RA4 MCUs support a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh that can contain program, data, and external memory bus. Program and data memory share the address space;... -
Page 30: Sram
Figure 22. RA4M3 Standby SRAM Specification The LPM (Low Power Mode) driver in Renesas FSP provides an option to cut or keep power to Standby SRAM as shown in the following figure. The LPM driver’s APIs still need to be invoked to write the selected settings to the MCU registers. -
Page 31: Peripheral I/O Registers
Flash I/O registers to control access flash memory occupy two regions, 407E 0000h to 407E FFFFh and 407F C000h to 407F FFFFh. The Renesas FSP provides C header files in CMSIS data structure that map all of the peripheral I/O registers for a specific device to easily accessible I/O data structures. -
Page 32: Background Operation
ID code is input. Refer to the “OCD/Serial Programmer ID Setting Register (OSIS)” and “ID Code Protection” and sections of RA4 MCU Hardware User’s Manual for more information. The Renesas FSP configurator provides options to set up ID code protection for RA4 MCUs with the Arm Cortex-M4 core. -
Page 33: Flash Block Protection
Renesas RA Family RA4 Quick Design Guide Figure 25. ID Code Setup for RA4M1 (Arm Cortex-M4 Core) Using Renesas FSP Configurator Note: ID code protection settings must be handled carefully to prevent mistakes that may result in blocking accesses to the MCU. -
Page 34: Restriction On Endianness
Renesas RA Family RA4 Quick Design Guide Figure 26. MPU Setup for RA4M1 (Arm Cortex-M4 core) Using Renesas FSP Configurator Note: MPU settings must be handled carefully to prevent mistakes that may result in blocking accesses to an MCU region. -
Page 35: I/O Port Configuration
Most pins on the RA4 Series of MCUs can be configured from a selection of multiple peripheral functions. Tools, such as the pin configurator in FSP, are available from Renesas to assist with assigning pins for each peripheral function. When several peripheral functions are needed, use the following design strategies to help with pin selection. -
Page 36: Setting Up And Using A Pin As Gpio
Using the PmnPFS registers will have more configuration features available but will have slower access. The Renesas FSP provides a Pin Configurator to configure GPIO pins after reset as shown below. After the GPIO is configured, it can be controlled using HAL layer APIs in FSP. -
Page 37: Internal Pull-Ups
Renesas RA Family RA4 Quick Design Guide 10.2.1 Internal Pull-Ups • Most pins on ports 0 through 9 have the option of enabling a pull-up resistor. The pull-up is controlled by the Pull-Up Control (PCR) bit in each Port mn Pin Function Select (PmnPFS) Register. The PCR bit in each PmnPFS register controls the corresponding pin on the port. -
Page 38: Setting Up And Using Port Peripheral Functions
MPC that must be configured before using these peripherals. • The figure below shows an example of enabling QSPI pins using FSP Pin configuration. Figure 29. Enabling QSPI pins Using Pin Configurator in Renesas FSP R01AN5988EU0100 Rev.1.00 Page 38 of 51... -
Page 39: Setting Up And Using Irq Pins
IRQ Pin Digital Filter Setting (FCLKSEL[1:0]) bits in the IRQCRi register for each IRQ. • Figure 30 and Figure 31 show examples of enabling and configuring IRQ pins using Renesas FSP. Figure 30. Enable P202, P000 as IRQ03, IRQ06 Inputs Respectively Using Pin Configurator in Renesas FSP R01AN5988EU0100 Rev.1.00... -
Page 40: Unused Pins
Renesas RA Family RA4 Quick Design Guide Figure 31. Configure IRQ13 using the Renesas FSP Configurator 10.5 Unused Pins Note: Some pins require specific termination: See the “Handling of Unused Pins” section of the Hardware User’s Manual for specific recommendations. -
Page 41: Nonexistent Pins
‘0’ to the corresponding bit in the MSTPCRi register. Peripherals may be stopped by writing a ‘1’ to the proper bit in the MSTPCRi register. HAL drivers in Renesas FSP handle module start/stop function automatically. 12. Interrupt Control Unit The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC, DTC, and DMAC modules. - Page 42 Figure 33. RA4M3 ICU I/O Pins The following figure is an example of using Renesas FSP configurator to enable and configure an interrupt using Renesas FSP. The ICU and interrupts are configured as part of the HAL driver configuration through FSP.
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Page 43: Low Power Consumption
Renesas RA Family RA4 Quick Design Guide Figure 34. Enable GTP0 Overflow Interrupt and Set User Callback Functions Which Will be Invoked by Interrupt Service Routine 13. Low Power Consumption The RA4 devices have several functions for reducing power consumption. These include setting clock dividers, stopping modules, selecting power control mode in Normal mode, and transitions to low power modes. - Page 44 Renesas RA Family RA4 Quick Design Guide Table 16. Specifications of the lower power mode functions Item Specification Reducing power consumption by modifying clock The frequency division ratio can be selected signals independently for the system clock (ICLK), peripheral module clock (PCLKA, PCLKB, PCLKC, PCLKD), and flash interface clock (FCLK).*...
- Page 45 The transitions to other LPMs are done by executing a WFI instruction with appropriate settings in the Standby Control register (SBYCR). Renesas FSP provides a low power mode (LPM) driver and driver configurator to set up low power mode, wake source/cancel source, and so forth.
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Page 46: Buses
Renesas RA Family RA4 Quick Design Guide /* Open LPM driver and initialize LPM mode */ err = R_LPM_Open(&g_lpm_deep_sw_standby_ctrl, &g_lpm_deep_sw_standby_cfg); /* Handle error */ if (FSP_SUCCESS != err) return (err); /* Transition to configured LPM mode: Deep Software Standby Mode */ err = R_LPM_LowPowerModeEnter(&g_lpm_deep_sw_standby_ctrl);... -
Page 47: Bus Error Monitoring
Renesas RA Family RA4 Quick Design Guide Figure 37. RA4M3 Bus Connection 14.1 Bus Error Monitoring The bus error monitoring system monitors each individual area. When an error is detected, an error is returned to the requesting master IP using the AHB-Lite error response protocol. -
Page 48: General Layout Practices
Due to the highly multiplexed nature of the I/O pins on Renesas RA4 MCU devices, many I/O pins can be used for either Analog or Digital functions. This can result in situations where digital and analog functions may overlap and result in data errors. -
Page 49: Signal Group Selections
The following documents were used in creating this Quick Design Guide. Visit the Renesas website for the latest version of each of these documents. Reference Document Number Description R01UH0887 Renesas RA4M1 Group, User’s Manual: Hardware R01UH0892 Renesas RA4M2 Group, User’s Manual: Hardware R01UH0893 Renesas RA4M3 Group, User’s Manual: Hardware ® ® R20AN0577... - Page 50 Renesas RA Family RA4 Quick Design Guide Website and Support Visit the following vanity URLs to learn about key elements of the RA family, download components and related documentation, and get support. 1. RA Product Information www.renesas.com/ra 2. RA Product Support Forum www.renesas.com/ra/forum...
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Page 51: Revision History
Renesas RA Family RA4 Quick Design Guide Revision History Description Rev. Date Page Summary 1.00 Jul.21.21 — Initial release R01AN5988EU0100 Rev.1.00 Page 51 of 51 Jul.21.21... - Page 52 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
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