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R8C/18 Group, R8C/19 Group
Voltage Monitor 2 Circuit Control Register
b7 b6 b5 b4
b3
b2
b1 b0
NOTES:
1.
Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to this register.
When rew riting the VW2C register, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the VW2C
register.
2.
When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite 0 to the VW2C1bit before
w riting 1.
3.
This bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
4.
Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5.
This bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enabled reset).
6.
The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
7.
The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).
8.
Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, or voltage monitor 2
9.
When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or
below ). (Do not set to 0.)
Set the VW2C0 bit to 0 (disabled) w hen the VCA13 bit in the VCA1 register is set to 1 (VCC ≥ Vdet2 or voltage
10.
detection 2 circuit disabled), the VW2C1 bit is set to 1 (digital filter disabled mode), and the VW2C7 bit is set to 0
(w hen VCC reaches Vdet2 or above).
Set the VW2C0 bit to 0 (disabled) w hen the VCA13 bit is set to 0 (VCC < Vdet2), the VW2C1 bit is set to 1 (digital
filter disabled mode), and the VW2C7 bit is set to 1 (w hen VCC reaches Vdet2 or below ).
Figure 7.6
VW2C Register
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
(1)
Symbol
Address
VW2C
0037h
Bit Symbol
Bit Name
Voltage monitor 2 interrupt/reset
VW2C0
(6, 10)
enable bit
Voltage monitor 2 digital filter
disable mode select bit
VW2C1
Voltage change detection flag
VW2C2
WDT detection flag
VW2C3
Sampling clock select bits
VW2F0
VW2F1
Voltage monitor 2 circuit mode
VW2C6
(5)
select bit
Voltage monitor 2 interrupt/reset
generation condition select bit
VW2C7
Page 45 of 233
0 : Disable
1 : Enable
0 : Digital filter enabled mode
(2)
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
(3, 4, 8)
0 : Not detected
1 : Vdet2 crossing detected
(4, 8)
0 : Not detected
1 : Detected
b5 b4
0 0 : fRING-S divide by 1
0 1 : fRING-S divide by 2
1 0 : fRING-S divide by 4
1 1 : fRING-S divide by 8
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode
0 : When VCC reaches Vdet2 or above.
(7, 9)
1 : When VCC reaches Vdet2 or below .
7. Voltage Detection Circuit
(8)
After Reset
00h
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
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