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Renesas R8C/32A Series Hardware Manual

M16c family / r8c/tiny series mcu

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REJ09B0458-0010

16

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Technology Corp. without notice. Please review the latest information published

by Renesas Technology Corp. through various means, including the Renesas Technology

Corp. website (http://www.renesas.com).

Rev.0.10

Revision Date: Apr 01, 2008

R8C/32A

Hardware Manual

RENESAS MCU

M16C FAMILY / R8C/Tiny SERIES

Preliminary

Group

www.renesas.com

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Summary of Contents for Renesas R8C/32A Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3: General Precautions In The Handling Of Mpu/Mcu Products
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4: How To Use This Manual
The following documents apply to the R8C/32A Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type...
Page 5: Notation Of Numbers And Symbols
Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,”...
Page 6 Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) Address XXXXh Symbol XXX7 XXX6 XXX5 XXX4 — — XXX1 XXX0 After Reset Symbol Bit Name Function XXX0 XXX bit b1 b0 0 0: XXX XXX1 0 1: XXX 1 0: Do not set.
Page 7: List Of Abbreviations And Acronyms
List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association Least Significant Bit...
Page 8: Table Of Contents
Table of Contents SFR Page Reference ........................... B - 1 Overview ............................1 Features ..............................1 1.1.1 Applications ............................1 1.1.2 Specifications ............................2 Product List ............................... 4 Block Diagram ............................5 Pin Assignment ............................6 Pin Functions ............................. 8 Central Processing Unit (CPU) .....................
Page 9 Cold Start-Up/Warm Start-Up Determination Function ................. 36 Reset Source Determination Function ..................... 36 Voltage Detection Circuit ......................37 Overview ..............................37 Registers ..............................41 6.2.1 Voltage Monitor Circuit/Comparator A Control Register (CMPA) ........... 41 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) ..............42 6.2.3 Voltage Detect Register (VCA1) ......................
Page 10 Bus ..............................87 Clock Generation Circuit ....................... 89 Overview ..............................89 Registers ..............................92 9.2.1 System Clock Control Register 0 (CM0) .................... 92 9.2.2 System Clock Control Register 1 (CM1) .................... 93 9.2.3 System Clock Control Register 3 (CM3) .................... 94 9.2.4 Oscillation Stop Detection Register (OCD) ..................
Page 11 10.1.1 Protect Register (PRCR) ........................120 Interrupts ............................. 121 11.1 Overview ............................... 121 11.1.1 Types of Interrupts ..........................121 11.1.2 Software Interrupts ........................... 122 11.1.3 Special Interrupts ..........................123 11.1.4 Peripheral Function Interrupts ......................123 11.1.5 Interrupts and Interrupt Vectors ......................124 11.2 Registers ..............................
Page 12 12.3 Forced Erase Function ........................... 150 12.4 Standard Serial II/O Mode Disabled Function ..................150 12.5 Notes on ID Code Areas ........................151 12.5.1 Setting Example of ID Code Areas ....................151 Option Function Select Area ....................... 152 13.1 Overview ............................... 152 13.2 Registers ..............................
Page 13 15.4 Notes on DTC ............................181 15.4.1 DTC activation source ........................181 15.4.2 DTCENi Registers (i = 0 to 3, 5, 6) ....................181 15.4.3 Peripheral Modules ........................... 181 General Overview of Timers ....................... 182 Timer RA ............................. 184 17.1 Overview ...............................
Page 14 18.5.2 Operating Example ........................... 214 18.5.3 One-Shot Trigger Selection ......................215 18.6 Programmable Wait One-Shot Generation Mode ................. 216 18.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode ... 217 18.6.2 Operating Example ........................... 218 18.7 Notes on Timer RB ..........................
Page 15 19.7 PWM2 Mode ............................258 19.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode .............. 260 19.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode .............. 261 19.7.3 Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode ......... 261 19.7.4 Operating Example ...........................
Page 16 21.3.1 Polarity Select Function ........................298 21.3.2 LSB First/MSB First Select Function ....................298 21.3.3 Continuous Receive Mode ........................ 299 21.4 Clock Asynchronous Serial I/O (UART) Mode ..................300 21.4.1 Bit Rate ............................. 305 21.5 Notes on Serial Interface (UART0) ....................... 306 Serial Interface (UART2) ......................
Page 17 22.6.1 Multiprocessor Transmission ......................346 22.6.2 Multiprocessor Reception ......................... 347 22.6.3 RXD2 Digital Filter Select Function ....................349 22.7 Notes on Serial Interface (UART2) ....................... 350 22.7.1 Clock Synchronous Serial I/O Mode ....................350 22.7.2 Clock Asynchronous Serial I/O (UART) Mode ................351 22.7.3 Special Mode 1 (I C Mode) ......................
Page 18 25.2.6 IIC bus Control Register 2 (ICCR2) ....................389 25.2.7 IIC bus Mode Register (ICMR) ......................390 25.2.8 IIC bus Interrupt Enable Register (ICIER) ..................391 25.2.9 IIC bus Status Register (ICSR) ......................392 25.2.10 Slave Address Register (SAR) ......................393 25.2.11 IIC bus Shift Register (ICDRS) ......................
Page 19 27.3.1 Input/Output Pins ..........................440 27.3.2 A/D Conversion Cycles ........................440 27.3.3 A/D Conversion Start Condition ....................... 442 27.3.4 A/D Conversion Result ........................443 27.3.5 Low Current Consumption Function ....................443 27.3.6 Extended Analog Input Pins ......................443 27.3.7 A/D Open-Circuit Detection Assist Function ................... 443 27.4 One-Shot Mode .............................
Page 20 30.3.1 ID Code Check Function ........................480 30.3.2 ROM Code Protect Function ......................481 30.3.3 Option Function Select Register (OFS) .................... 481 30.4 CPU Rewrite Mode ..........................482 30.4.1 Flash Memory Status Register (FST) ....................483 30.4.2 Flash Memory Control Register 0 (FMR0) ..................485 30.4.3 Flash Memory Control Register 1 (FMR1) ..................
Page 21 33.1.2 Wait Mode ............................545 33.1.3 Oscillation Stop Detection Function ....................545 33.1.4 Oscillation Circuit Constants ......................545 33.2 Notes on Interrupts ..........................546 33.2.1 Reading Address 00000h ........................546 33.2.2 SP Setting ............................546 33.2.3 External Interrupt and Key Input Interrupt ..................546 33.2.4 Changing Interrupt Sources ......................
Page 22 33.17.2 Countermeasures against Noise Error of Port Control Registers ............. 566 Notes on On-Chip Debugger ...................... 567 Appendix 1. Package Dimensions ......................568 Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator .... 569 Appendix 3. Example of Oscillation Evaluation Circuit ................. 570 Index ..............................
Page 23 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0000h 0040h 0001h 0041h Flash Memory Ready Interrupt Control FMRDYIC Register 0002h 0042h 0003h 0043h 0004h Processor Mode Register 0 0044h 0005h Processor Mode Register 1 0045h 0006h System Clock Control Register 0 0046h 0007h System Clock Control Register 1...
Page 24 Address Register Symbol Page Address Register Symbol Page 0080h DTC Start Control Register DTCTL 00C0h A/D Register 0 0081h 00C1h 0082h 00C2h A/D Register 1 0083h 00C3h 0084h 00C4h A/D Register 2 0085h 00C5h 0086h 00C6h A/D Register 3 0087h 00C7h 0088h DTC Start Enable Register 0...
Page 25 Address Register Symbol Page Address Register Symbol Page 0100h Timer RA Control Register TRACR 0140h 0101h Timer RA I/O Control Register TRAIOC 185, 188, 191, 0141h 193, 195, 198 0142h 0102h Timer RA Mode Register TRAMR 0143h 0103h Timer RA Prescaler Register TRAPRE 0144h 0104h...
Page 26 Address Register Symbol Page Address Register Symbol Page 0180h Timer RA Pin Select Register TRASR 67, 187 01C0h Address Match Interrupt Register 0 RMAD0 0181h Timer RC Pin Select Register TRBRCSR 67, 231 01C1h 0182h Timer RC Pin Select Register 0 TRCPSR0 68, 232 01C2h...
Page 27 Address Register Symbol Page Address Register Symbol Page 2C00h DTC Transfer Vector Area 2C70h DTCD6 2C01h DTC Transfer Vector Area 2C71h 2C02h DTC Transfer Vector Area 2C72h 2C03h DTC Transfer Vector Area 2C73h 2C04h DTC Transfer Vector Area 2C74h 2C05h DTC Transfer Vector Area 2C75h 2C06h...
Page 28 Address Register Symbol Page Address Register Symbol Page 2CB0h DTCD14 2CF0h DTCD22 2CB1h 2CF1h 2CB2h 2CF2h 2CB3h 2CF3h 2CB4h 2CF4h 2CB5h 2CF5h 2CB6h 2CF6h 2CB7h 2CF7h 2CB8h DTCD15 2CF8h DTCD23 2CB9h 2CF9h 2CBAh 2CFAh 2CBBh 2CFBh 2CBCh 2CFCh 2CBDh 2CFDh 2CBEh 2CFEh 2CBFh...
Page 29: Overview
PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. R8C/32A Group REJ09B0458-0010 RENESAS MCU Rev.0.10 Apr 01, 2008 Overview Features The R8C/32A Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency.
Page 30: Specifications
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/32A Group. Table 1.1 Specifications for R8C/32A Group (1) Item Function Specification Central processing R8C/Tiny series core unit...
Page 31 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview Table 1.2 Specifications for R8C/32A Group (2) Item Function Specification Serial UART0 Clock synchronous serial I/O/UART Interface UART2 Clock synchronous serial I/O/UART, I C mode (I C-bus), multiprocessor communication function...
Page 32: Product List
1: 4 KB 2: 8 KB 4: 16 KB R8C/32A Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/32A Group REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 4 of 572...
Page 33: Block Diagram
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview Block Diagram Figure 1.2 shows a Block Diagram. I/O ports Port P1 Port P3 Port P4 Peripheral functions UART or Timers clock synchronous serial I/O System clock generation (8 bits ×...
Page 34: Pin Assignment
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number. P1_0/AN8/LVCMP1/KI0(/TRCIOD) P4_2/VREF MODE P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG) P1_2/AN10/LVREF/Kl2(/TRCIOB) RESET...
Page 35 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview Table 1.4 Pin Name Information by Pin Number I/O Pin Functions for Peripheral Modules A/D Converter, Control Pin Port Serial Comparator A, Number Interrupt Timer...
Page 36: Pin Functions
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview Pin Functions Tables 1.5 and 1.6 list Pin Functions. Table 1.5 Pin Functions (1) Item Pin Name I/O Type Description − Power supply input VCC, VSS Apply 1.8 V to 5.5 V to the VCC pin.
Page 37 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1. Overview Table 1.6 Pin Functions (2) Item Pin Name I/O Type Description Reference voltage input VREF Reference voltage input pin to A/D converter A/D converter AN8 to AN11 Analog input pins to A/D converter...
Page 38: Central Processing Unit (Cpu)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank.
Page 39: Data Registers (R0, R1, R2, And R3)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
Page 40: Interrupt Enable Flag (I)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
Page 41: Memory
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 3. Memory Memory R8C/32A Group Figure 3.1 is a Memory Map of R8C/32A Group. The R8C/32A Group has a 1-Mbyte address space from addresses 00000h to FFFFFh.
Page 42: Special Function Registers (Sfrs)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers.
Page 43 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) Address Register Symbol After Reset 003Ah Voltage Monitor 2 Circuit Control Register VW2C 10000010b 003Bh 003Ch 003Dh...
Page 44 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3) Address Register Symbol After Reset 0080h DTC Activation Control Register DTCTL 0081h 0082h 0083h 0084h 0085h 0086h...
Page 45 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) Address Register Symbol After Reset 00C0h A/D Register 0 XXXh 000000XXb 00C1h 00C2h A/D Register 1 00C3h 000000XXb 00C4h...
Page 46 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5) Address Register Symbol After Reset 0100h Timer RA Control Register TRACR 0101h Timer RA I/O Control Register TRAIOC 0102h Timer RA Mode Register...
Page 47 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) Address Register Symbol After Reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh...
Page 48 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) Address Register Symbol After Reset 0180h Timer RA Pin Select Register TRASR 0181h Timer RC Pin Select Register TRBRCSR 0182h Timer RC Pin Select Register 0...
Page 49 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.8 SFR Information (8) Address Register Symbol After Reset 01C0h Address Match Interrupt Register 0 RMAD0 01C1h 01C2h 0000XXXXb 01C3h Address Match Interrupt Enable Register 0...
Page 50 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.9 SFR Information (9) Address Register Symbol After Reset 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h...
Page 51 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.10 SFR Information (10) Address Register Symbol After Reset 2C70h DTC Control Data 6 DTCD6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h...
Page 52 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.11 SFR Information (11) Address Register Symbol After Reset 2CB0h DTC Control Data 14 DTCD14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h...
Page 53 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) Table 4.12 SFR Information (12) Address Register Symbol After Reset 2CF0h DTC Control Data 22 DTCD22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h...
Page 54: Resets
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources and Figure 5.1 shows the Block Diagram of Reset Circuit. Table 5.1 Reset Names and Sources Reset Name...
Page 55: Pin Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence. Table 5.2 Pin Functions while RESET Pin Level is “L”...
Page 56: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Registers 5.1.1 Processor Mode Register 0 (PM0) Address 0004h Symbol — — — — PM03 — — — After Reset Symbol Bit Name Function —...
Page 57: Option Function Select Register (Ofs)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets 5.1.3 Option Function Select Register (OFS) Address 0FFFFh Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON When shipping (Note 1) Symbol Bit Name Function WDTON Watchdog timer start select bit...
Page 58: Option Function Select Register 2 (Ofs2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets 5.1.4 Option Function Select Register 2 (OFS2) Address 0FFDBh Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping (Note 1) Symbol Bit Name Function...
Page 59: Hardware Reset
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions while RESET Pin Level is “L”).
Page 60 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets 1.8 V RESET RESET 0.2 VCC or below td(P-R) + 10 µs or more Note: 1. Refer to 32. Electrical Characteristics. Figure 5.4 Example of Hardware Reset Circuit and Operation Supply voltage detection circuit...
Page 61: Power-On Reset Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
Page 62: Voltage Monitor 0 Reset
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin.
Page 63: Watchdog Timer Reset
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows.
Page 64: Cold Start-Up/Warm Start-Up Determination Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets Cold Start-Up/Warm Start-Up Determination Function The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation.
Page 65: Voltage Detection Circuit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Voltage Detection Circuit The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program.
Page 66 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Shared with comparator A VCA27 VCA24 = 1 LVCMP2 Voltage detection 2 signal VCA24 = 0 ≥ Vdet2 VCA1 register VCA13 bit VCA26 Level...
Page 67 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Voltage monitor 0 reset generation circuit VW0F1 to VW0F0 = 00b = 01b = 10b Voltage detection 0 circuit = 11b fOCO-S VCA25 VW0C1...
Page 68 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Voltage monitor 2 interrupt generation circuit VW2F1 to VW2F0 = 00b = 01b Voltage detection 2 circuit = 10b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), = 11b fOCO-S...
Page 69: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Registers 6.2.1 Voltage Monitor Circuit/Comparator A Control Register (CMPA) Address 0030h Symbol COMPSEL — IRQ2SEL IRQ1SEL CM2OE CM1OE CM2POR CM1POR After Reset Symbol Bit Name...
Page 70: Voltage Monitor Circuit Edge Select Register (Vcac)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) Address 0031h Symbol — — — — — VCAC2 VCAC1 — After Reset Symbol Bit Name Function...
Page 71: Voltage Detect Register 2 (Vca2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.4 Voltage Detect Register 2 (VCA2) Address 0034h Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. After Reset The LVDAS bit in the OFS register is set to 0.
Page 72: Voltage Detection 1 Level Select Register (Vd1Ls)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) Address 0036h Symbol — — — — VD1S3 VD1S2 VD1S1 VD1S0 After Reset Symbol Bit Name Function...
Page 73: Voltage Monitor 0 Circuit Control Register (Vw0C)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) Address 0038h Symbol — — VW0F1 VW0F0 — — VW0C1 VW0C0 After Reset The LVDAS bit in the OFS register is set to 1. After Reset The LVDAS bit in the OFS register is set to 0.
Page 74: Voltage Monitor 1 Circuit Control Register (Vw1C)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) Address 0039h Symbol VW1C7 — VW1F1 VW1F0 VW1C3 VW1C2 VW1C1 VW1C0 After Reset Symbol Bit Name Function...
Page 75: Voltage Monitor 2 Circuit Control Register (Vw2C)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) Address 003Ah Symbol VW2C7 — VW2F1 VW2F0 VW2C3 VW2C2 VW2C1 VW2C0 After Reset Symbol Bit Name Function...
Page 76: Option Function Select Register (Ofs)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit 6.2.9 Option Function Select Register (OFS) Address 0FFFFh Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON When shipping (Note 1) Symbol Bit Name Function...
Page 77: Vcc Input Voltage
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit VCC Input Voltage 6.3.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.3.2 Monitoring Vdet1 Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 32.
Page 78: Voltage Monitor 0 Reset
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Voltage Monitor 0 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.5 shows an Operating Example of Voltage Monitor 0 Reset.
Page 79: Voltage Monitor 1 Interrupt
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Voltage Monitor 1 Interrupt Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of Voltage Monitor 1 Interrupt.
Page 80 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Vdet1 1.8 V VW1C3 bit Sampling clock of Sampling clock of digital filter × 2 cycles digital filter × 2 cycles VW1C2 bit VW1C1 bit is set to 0 (digital filter enabled)
Page 81: Voltage Monitor 2 Interrupt
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit Voltage Monitor 2 Interrupt Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of Voltage Monitor 2 Interrupt.
Page 82 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit VCC or LVCMP2 Vdet2 1.8 V VW1C3 bit Sampling clock of Sampling clock of digital filter × 2 cycles digital filter × 2 cycles VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled)
Page 83: I/O Ports
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports I/O Ports There are 15 I/O ports P1, P3_3 to P3_5, P3_7, and P4_5 to P4_7 (P4_6 and P4_7 can be used as I/O ports if the XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used.).
Page 84: Effect On Peripheral Functions
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Effect on Peripheral Functions I/O ports function as I/O ports for peripheral functions (Refer to Table 1.4 Pin Name Information by Pin Number).
Page 85: Configuration Of I/O Ports
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P1_0 to P1_2 Drive capacity selection Pull-up selection Direction register Pin select register (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input level...
Page 86 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P1_4 Drive capacity selection Pull-up selection Direction register Pin select register (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input level switch function...
Page 87 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P1_6 Drive capacity selection Pull-up selection Direction register Pin select register (Note 1) Output from individual peripheral function Port latch Data bus (Note 1) Input level switch function...
Page 88 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P3_3 Drive capacity selection Pull-up selection Direction register Pin select register (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input level switch function...
Page 89 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P3_5 Drive capacity selection Pull-up selection Direction register Pin select register (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input level switch function...
Page 90 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P4_2/VREF (Note 1) Input level Data bus switch function (Note 1) P4_5 Drive capacity selection Pull-up selection Direction register Pin select register (Note 1) Output from individual...
Page 91 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports P4_6/XIN/XCIN Drive capacity selection Pull-up selection Direction register (Note 1) Data bus Port latch (Note 1) CM01 Input level CM13 CM04, CM13 switch function Drive capacity selection CM11...
Page 92 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports MODE MODE signal input (Note 1) RESET (Note 1) RESET signal input (Note 1) Note: symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.8 Configuration of I/O Pins REJ09B0458-0010 Rev.0.10...
Page 93: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Registers 7.4.1 Port Pi Direction Register (PDi) (i = 1, 3, 4) Address 00E3h (PD1), 00E7h (PD3 ), 00EAh (PD4 Symbol PDi_7 PDi_6 PDi_5...
Page 94: Port Pi Register (Pi) (I = 1, 3, 4)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.2 Port Pi Register (Pi) (i = 1, 3, 4) Address 00E1h(P1), 00E5h(P3 ), 00E8h(P4 Symbol Pi_7 Pi_6 Pi_5 Pi_4 Pi_3 Pi_2 Pi_1 Pi_0...
Page 95: Timer Ra Pin Select Register (Trasr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.3 Timer RA Pin Select Register (TRASR) Address 0180h Symbol — — — — — — TRAIOSEL1 TRAIOSEL0 After Reset Symbol Bit Name Function TRAIOSEL0 TRAIO pin select bit...
Page 96: Timer Rc Pin Select Register 0 (Trcpsr0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Symbol — — — TRCIOBSEL0 — — — TRCIOASEL0 After Reset Symbol Bit Name Function...
Page 97: Uart0 Pin Select Register (U0Sr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.7 UART0 Pin Select Register (U0SR) Address 0188h Symbol — — — CLK0SEL0 — RXD0SEL0 — TXD0SEL0 After Reset Symbol Bit Name Function TXD0SEL0 TXD0 pin select bit 0: TXD0 pin not used...
Page 98: Uart2 Pin Select Register 0 (U2Sr0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.8 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Symbol — — RXD2SEL1 RXD2SEL0 — — TXD2SEL1 TXD2SEL0 After Reset Symbol Bit Name Function TXD2SEL0 TXD2/SDA2 pin select bit...
Page 99: Ssu/Iic Pin Select Register (Ssuiicsr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.10 SSU/IIC Pin Select Register (SSUIICSR) Address 018Ch Symbol — — — — — — — IICSEL After Reset Symbol Bit Name Function IICSEL 0: SSU function selected...
Page 100: Pull-Up Control Register 0 (Pur0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.12 Pull-Up Control Register 0 (PUR0) Address 01E0h Symbol PU07 PU06 — — PU03 PU02 — — After Reset Symbol Bit Name Function —...
Page 101: Port P1 Drive Capacity Control Register (P1Drr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.14 Port P1 Drive Capacity Control Register (P1DRR) Address 01F0h Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0 After Reset Symbol Bit Name Function...
Page 102: Drive Capacity Control Register 0 (Drr0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.15 Drive Capacity Control Register 0 (DRR0) Address 01F2h Symbol DRR07 DRR06 — — — — — — After Reset Symbol Bit Name Function —...
Page 103: Drive Capacity Control Register 1 (Drr1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.16 Drive Capacity Control Register 1 (DRR1) Address 01F3h Symbol — — — — — — DRR11 — After Reset Symbol Bit Name Function —...
Page 104: Input Threshold Control Register 0 (Vlt0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports 7.4.17 Input Threshold Control Register 0 (VLT0) Address 01F5h Symbol VLT07 VLT06 — — VLT03 VLT02 — — After Reset Symbol Bit Name Function —...
Page 105: Port Settings
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Port Settings Tables 7.4 to 7.24 list the port settings. Table 7.4 Port P1_0/KI0/AN8/TRCIOD/LVCMP1 Register KIEN ADINSEL TRCPSR1 VCA2 Timer RC Setting ADGSEL TRCIODSEL Function...
Page 106 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.6 Port P1_2/KI2/AN10/TRCIOB/LVREF Timer RC Register KIEN ADINSEL TRCPSR0 VCA2 Setting Function ADGSEL PD1_2 KI2EN TRCIOBSEL0 VCA21 VCA23 — Input port Output port KI2 input A/D converter input (AN10)
Page 107 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.8 Port P1_4/TXD0/TRCCLK Register U0SR U1MR TRBRCSR TRCCR1 TRCCLKSEL Function PD1_4 TXD0SEL0 Input port Output port Setting Value (2, 3) TXD0 output TRCCLK input X: 0 or 1...
Page 108 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.11 Port P1_7/INT1/TRAIO/IVCMP1 Register TRASR TRAIOC TRAMR INTSR INTEN INTCMP TRAIOSEL TMOD INT1SEL Function PD1_7 TOPCR INT1EN INT1CP0 Other than 01b Input port Other than 01b Output port...
Page 109 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.13 Port P3_4/TRCIOC/SSI/RXD2/SCL2/TXD2/SDA2/IVREF3 Synchronous Serial Communication Unit (Refer to Table 24.4 Timer RC Register PD3 SSUIICSR TRCPSR1 U2SR0 U2MR U2SMR INTCMP Association between Setting Communication...
Page 110 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.14 Port P3_5/SCL/SSCK/TRCIOD/CLK2 Synchronous Serial Communication Unit (Refer Timer RC Register SSUIICSR ICCR1 to Table 24.4 Association TRCPSR1 U2SR1 U2MR Setting between Communication Function...
Page 111 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.16 Port P4_2/VREF Register ADCON1 Function ADSTBY Input port Setting Value Input port/VREF input Table 7.17 Port P4_5/INT0/RXD2/SCL2/ADTRG Register INTEN U2SR0 U2MR U2SMR...
Page 112 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.19 Port P4_7/XOUT/XCOUT Register Circuit specifications Function Oscillation Feedback PD4_7 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13 buffer resistor Input port Output port XIN-XOUT oscillation...
Page 113 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Table 7.20 TRBO Pin Setting Register TRBIOC TRBMR Function TMOD1 TMOD0 TOCNT Programmable waveform generation mode Programmable one-shot generation mode Setting value Programmable wait one-shot generation mode Programmable output port...
Page 114: Unassigned Pin Handling
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports Unassigned Pin Handling Table 7.25 lists Unassigned Pin Handling. Figure 7.9 shows the Unassigned Pin Handling. Table 7.25 Unassigned Pin Handling Pin Name Connection Ports P1, P3_3 to P3_5,...
Page 115: Bus
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 8. Bus The bus cycles differ when accessing ROM/RAM and when accessing SFR. Table 8.1 lists Bus Cycles by Access Area of R8C/32A Group (with Data Flash). ROM/RAM and SFR are connected to the CPU by an 8-bit bus.
Page 116 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 8. Bus However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2, and U2SMR...
Page 117: Clock Generation Circuit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit: • XIN clock oscillation circuit • XCIN clock oscillation circuit •...
Page 118 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Low-speed on-chip oscillator CSPRO fOCO-WDT for watchdog timer fC32 FRA1 register Frequency adjustable High-speed FRA00 fOCO40M on-chip oscillator FRA2 register Divider fOCO-F FRA01 = 1...
Page 119 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit fC32 fOCO40M fOCO128 fOCO fOCO-F Watchdog fOCO-WDT timer SSU / C bus A/D converter INT0 Timer RA Timer RB Timer RC Timer RE UART0 UART2...
Page 120: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Registers 9.2.1 System Clock Control Register 0 (CM0) Address 0006h Symbol CM07 CM06 CM05 CM04 CM03 CM02 CM01 — After Reset Symbol Bit Name Function...
Page 121: System Clock Control Register 1 (Cm1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 1 (CM1) Address 0007h Symbol CM17 CM16 — CM14 CM13 CM12 CM11 CM10 After Reset Symbol Bit Name Function...
Page 122: System Clock Control Register 3 (Cm3)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.3 System Clock Control Register 3 (CM3) Address 0009h Symbol CM37 CM36 CM35 — — — — CM30 After Reset Symbol Bit Name Function...
Page 123: Oscillation Stop Detection Register (Ocd)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.4 Oscillation Stop Detection Register (OCD) Address 000Ch Symbol — — — — OCD3 OCD2 OCD1 OCD0 After Reset Symbol Bit Name Function OCD0 Oscillation stop detection enable bit...
Page 124: High-Speed On-Chip Oscillator Control Register 0 (Fra0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) Address 0023h Symbol — — — — FRA03 — FRA01 FRA00 After Reset Symbol Bit Name Function...
Page 125: High-Speed On-Chip Oscillator Control Register 2 (Fra2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) Address 0025h Symbol — — — — — FRA22 FRA21 FRA20 After Reset Symbol Bit Name Function...
Page 126: High-Speed On-Chip Oscillator Control Register 4 (Fra4)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4) Address 0029h Symbol — — — — — — — — After Reset When shipping Function b7-b0 36.864 MHz frequency correction data is stored.
Page 127: Voltage Detect Register 2 (Vca2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.2.14 Voltage Detect Register 2 (VCA2) Address 0034h Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. After Reset The LVDAS bit in the OFS register is set to 0.
Page 128 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Exit wait mode by interrupt (Note 1) Procedure for enabling reduced internal In interrupt routine power consumption using VCA20 bit VCA20 ←...
Page 129: Xin Clock
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit The clocks generated by the clock generation circuits are described below. XIN Clock The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.
Page 130: On-Chip Oscillator Clock
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit On-Chip Oscillator Clock The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register. 9.4.1 Low-Speed On-Chip Oscillator Clock The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,...
Page 131: Xcin Clock
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit XCIN Clock The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.
Page 132: Cpu Clock And Peripheral Function Clock
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit (With XIN and XCIN Pins Shared).
Page 133: Foco-S
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.6.7 fOCO-S fOCO-S is an operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low- speed on-chip oscillator on).
Page 134: Power Control
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode.
Page 135 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.7.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on), fOCO can be used for timer RA.
Page 136: Wait Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.7.2 Wait Mode Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when count source protection mode is disabled stop.
Page 137 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.7.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does not stop in wait mode), the peripheral function interrupts other than A/D conversion interrupts can be used to exit wait mode.
Page 138 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Figure 9.6 shows the Time from Wait Mode to Interrupt Routine Execution after CM30 Bit in CM3 Register is Set to 1 (MCU Enters Wait Mode). To use a peripheral function interrupt to exit wait mode, set up the following before setting the CM30 bit to 1.
Page 139 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction.
Page 140: Stop Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.7.3 Stop Mode Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop and the CPU and the peripheral functions operating with these clocks also stop.
Page 141: Exiting Stop Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.7.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1.
Page 142 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Figure 9.9 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Reset Standard operating mode Low-speed on-chip oscillator mode CM07 = 0 CM14 = 0...
Page 143: Oscillation Stop Detection Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 9.5 lists the Specifications of Oscillation Stop Detection Function.
Page 144: How To Use Oscillation Stop Detection Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit 9.8.1 How to Use Oscillation Stop Detection Function • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt.
Page 145 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Table 9.6 Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Bit Indicating Interrupt Source Oscillation stop detection...
Page 146 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Determination of Interrupt sources OCD3 = 1? (XIN clock stops) OCD1 = 1 (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock)? VW2C3 = 1?
Page 147: Notes On Clock Generation Circuit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit Notes on Clock Generation Circuit 9.9.1 Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode).
Page 148: 10. Protection
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 10. Protection 10. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows: •...
Page 149: 11. Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11. Interrupts 11.1 Overview 11.1.1 Types of Interrupts Figure 11.1 shows the Types of Interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (non-maskable interrupts)
Page 150: Software Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 11.1.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when the UND instruction is executed. 11.1.2.2 Overflow Interrupt An overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO...
Page 151: Special Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.1.3 Special Interrupts Special interrupts are non-maskable. 11.1.3.1 Watchdog Timer Interrupt A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer. 11.1.3.2 Oscillation Stop Detection Interrupt An oscillation stop detection interrupt is generated by the oscillation stop detection function.
Page 152: Interrupts And Interrupt Vectors
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Page 153 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Table 11.2 Relocatable Vector Tables Software...
Page 154: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.2 Registers 11.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0056h (TRAIC), 0058h (TRBIC), 005Eh (U2BCNIC), 0072h (VCMP1IC), 0073h (VCMP2IC), Symbol...
Page 155: Interrupt Control Register (Fmrdyic Trcic, Ssuic/Iicic)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.2.2 Interrupt Control Register (FMRDYIC TRCIC, SSUIC/IICIC) Address 0041h (FMRDYIC), 0047h (TRCIC), 004Fh (SSUIC/IICIC Symbol — — — — ILVL2 ILVL1 ILVL0 After Reset Symbol Bit Name...
Page 156: Inti Interrupt Control Register (Intiic) (I = 0, 1, 3)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.2.3 INTi Interrupt Control Register (INTiIC) (i = 0, 1, 3) Address 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) Symbol — — — ILVL2 ILVL1 ILVL0...
Page 157: Interrupt Control
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.3 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskable interrupt.
Page 158: Interrupt Sequence
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.3.4 Interrupt Sequence The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level after the instruction is completed.
Page 159: Interrupt Response Time
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.3.5 Interrupt Response Time Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response time includes the period from when an interrupt request is generated until the currently executing instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence (20 cycles, refer to (b) in Figure 11.4).
Page 160: Saving Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.3.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved on the stack, the 16 low-order bits in the PC are saved.
Page 161 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 11.6 shows the Register Saving Operation.
Page 162: Returning From Interrupt Routine
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.3.8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved on the stack, are automatically restored.
Page 163: 11.3.10 Interrupt Priority Level Selection Circuit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.3.10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 11.8 shows the Interrupt Priority Level Selection Circuit. Highest Priority level of interrupts Level 0 (initial value)
Page 164: Int Interrupt
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.4 INT Interrupt 11.4.1 INTi Interrupt (i = 0, 1, 3) The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register is to 1 (enabled).
Page 165: External Input Enable Register 0 (Inten)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.4.3 External Input Enable Register 0 (INTEN) Address 01FAh Symbol INT3PL INT3EN — — INT1PL INT1EN INT0PL INT0EN After Reset Symbol Bit Name Function INT0EN INT0 input enable bit 0: Disabled...
Page 166: Inti Input Filter (I = 0, 1, 3)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.4.5 INTi Input Filter (i = 0, 1, 3) The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in the INTF register.
Page 167: Key Input Interrupt
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.5 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode.
Page 168: Key Input Enable Register 0 (Kien)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.5.1 Key Input Enable Register 0 (KIEN) Address 01FEh Symbol KI3PL KI3EN KI2PL KI2EN KI1PL KI1EN KI0PL KI0EN After Reset Symbol Bit Name Function KI0EN KI0 input enable bit...
Page 169: Address Match Interrupt
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.6 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When the on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1, and fixed vector tables) in the user system.
Page 170: Address Match Interrupt Enable Register I (Aieri) (I = 0 Or 1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1) Address 01C3h (AIER0), 01C7h (AIER1) Symbol — — — —...
Page 171: Timer Rc Interrupt, Synchronous Serial Communication Unit Interrupt, I 2 C Bus Interface Interrupt, And Flash Memory Interrupt (Interrupts With Multiple Interrupt Request Sources)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.7 Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) The timer RC interrupt, synchronous serial communication unit interrupt, I C bus interface interrupt, and flash memory interrupt each have multiple interrupt request sources.
Page 172 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts As with other maskable interrupts, the timer RC interrupt, synchronous serial communication unit interrupt, I bus interface interrupt, and flash memory interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL.
Page 173: Notes On Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.8 Notes on Interrupts 11.8.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence.
Page 174: Changing Interrupt Sources
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.8.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes.
Page 175: Rewriting Interrupt Control Register
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.8.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that register are generated. If an interrupt request may be generated, disable the interrupt before rewriting the contents of the interrupt control register.
Page 176: 12. Id Code Areas
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12. ID Code Areas 12. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode.
Page 177: Functions
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12. ID Code Areas 12.2 Functions The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial programmer or the on-chip debugging emulator are checked to see if they match.
Page 178: Forced Erase Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12. ID Code Areas 12.3 Forced Erase Function This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the on- chip debugging emulator are “ALeRASE”...
Page 179: Notes On Id Code Areas
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12. ID Code Areas 12.5 Notes on ID Code Areas 12.5.1 Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction.
Page 180: 13. Option Function Select Area
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13. Option Function Select Area 13. Option Function Select Area 13.1 Overview The option function select area is used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation.
Page 181: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13. Option Function Select Area 13.2 Registers Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation.
Page 182: Option Function Select Register 2 (Ofs2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13. Option Function Select Area 13.2.2 Option Function Select Register 2 (OFS2) Address 0FFDBh Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping (Note 1) Symbol Bit Name...
Page 183: Notes On Option Function Select Area
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13. Option Function Select Area 13.3 Notes on Option Function Select Area 13.3.1 Setting Example of Option Function Select Area As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction.
Page 184: 14. Watchdog Timer
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system.
Page 185: Watchdog Timer Block Diagram
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer Prescaler CM07 = 0, WDTC7 = 0 1/16 CSPRO = 0 PM12 = 0 1/128 CPU clock Watchdog timer CM07 = 0, interrupt request WDTC7 = 1 Watchdog timer...
Page 186: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.2 Registers 14.2.1 Processor Mode Register 1 (PM1) Address 0005h Symbol — — — — — PM12 — — After Reset Symbol Bit Name Function...
Page 187: Watchdog Timer Control Register (Wdtc)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.2.4 Watchdog Timer Control Register (WDTC) Address 000Fh Symbol WDTC7 — — — — — — — After Reset Symbol Bit Name Function —...
Page 188: Option Function Select Register (Ofs)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.2.6 Option Function Select Register (OFS) Address 0FFFFh Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON When shipping (Note 1) Symbol Bit Name Function...
Page 189: Option Function Select Register 2 (Ofs2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.2.7 Option Function Select Register 2 (OFS2) Address 0FFDBh Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping (Note 1) Symbol Bit Name Function...
Page 190: Functional Description
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.3 Functional Description 14.3.1 Common Items for Multiple Modes 14.3.1.1 Refresh Acknowledgment Period The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can be selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register.
Page 191: Count Source Protection Mode Disabled
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.3.2 Count Source Protection Mode Disabled The count source for the watchdog timer is the CPU clock when count source protection mode is disabled. Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled).
Page 192: Count Source Protection Mode Enabled
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer 14.3.3 Count Source Protection Mode Enabled The count source for the watchdog timer is the low-speed on-chip oscillator clock for the watchdog timer when count source protection mode is enabled.
Page 193: 15. Dtc
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15. DTC The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrupt to perform data transfers.
Page 194: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC DTCCR: DTC control register DTCCR DTBLS: DTC block size register DTCENi DTCCT: DTC transfer count register DTC activation DTBLS (i = 0 to 3, 5, 6) DTRLD: DTC transfer count reload register request DTSAR: DTC source address register...
Page 195: Dtc Control Register (Dtccr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.2.1 DTC Control Register (DTCCR) Address See Table 15.5 Control Data Allocation Addresses. Symbol — — RPTINT CHNE DAMOD SAMOD RPTSEL MODE After Reset Symbol Bit Name...
Page 196: Dtc Transfer Count Register (Dtcct)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.2.3 DTC Transfer Count Register (DTCCT) Address See Table 15.5 Control Data Allocation Addresses. Symbol — — — — — — — —...
Page 197: Dtc Activation Enable Registers (Dtceni) (I = 0 To 3, 5, 6)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.2.7 DTC Activation Enable Registers (DTCENi) (i = 0 to 3, 5, 6) Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Dh (DTCEN5), 008Eh (DTCEN6) Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 —...
Page 198: Dtc Activation Control Register (Dtctl)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.2.8 DTC Activation Control Register (DTCTL) Address 0080h Symbol — — — — — — NMIF — After Reset Symbol Bit Name Function —...
Page 199: Function Description
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3 Function Description 15.3.1 Overview When the DTC is activated, control data is read from the DTC control data area to perform data transfers and control data after data transfer is written back to the DTC control data area.
Page 200 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC Table 15.4 DTC Activation Sources and Interrupt Source Flags for Setting to 0 at Data Transfer Completion DTC activation source generation Interrupt Source Flag for Setting to 0 ICSR register/RDRF bit in SSSR register C bus/SSU receive data full ICSR register/TDRE bit in SSSR register...
Page 201: Control Data Allocation And Dtc Vector Table
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3.3 Control Data Allocation and DTC Vector Table Control data is allocated in the order: Registers DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR. Table 15.5 shows the Control Data Allocation Addresses.
Page 202 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC When the DTC is activated, one control data is selected according to the data read from the vector table which has been assigned to each activation source, and the selected control data is read from the DTC control data area.
Page 203 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC DTC activation source generation NMIF = 1? Read DTC vector Read control data Transfer data Write back control data Branch 1 On completion of DTC transfer (on completion of the first DTC transfer in chain transfers), 0 is written to the bit among bits DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 and an CHNE = 1?
Page 204: Normal Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3.4 Normal Mode One to 256 bytes of data are transferred by one activation. The number of transfer times can be 1 to 256. When the specified number of transfer times is completed, an interrupt request is generated for the CPU.
Page 205: Repeat Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3.5 Repeat Mode One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be specified as the repeat area.
Page 206: Chain Transfers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3.6 Chain Transfers When the CHNE bit in the DTCCR register is 1 (chain transfers enabled), multiple data transfers can be continuously performed by one activation source. Figure 15.6 shows a Flow of Chain Transfers. When the DTC is activated, one control data is selected according to the data read from the DTC vector address corresponding to the activation source, and the selected control data is read from the DTC control data area.
Page 207: Operation Timings
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3.8 Operation Timings The DTC requires four clock cycles to read control data allocated in the DTC control data area. The number of clock cycles required to write back control data differs depending on the control data settings.
Page 208: Number Of Dtc Execution Cycles
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.3.9 Number of DTC Execution Cycles Table 15.10 shows the Operations Following DTC Activation and Required Number of Cycles for each operation. Table 15.11 shows the Number of Clock Cycles Required for Data Transfers.
Page 209: Notes On Dtc
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC 15.4 Notes on DTC 15.4.1 DTC activation source • Do not generate any DTC activation sources before entering wait mode or during wait mode. •...
Page 210: 16. General Overview Of Timers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 16. General Overview of Timers 16. General Overview of Timers The MCU has two 8-bit timers with 8-bit prescalers, a 16-bit timer, and a timer with a 4-bit counter and an 8-bit counter.
Page 211 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 16. General Overview of Timers Table 16.1 Functional Comparison of Timers Item Timer RA Timer RB Timer RC Timer RE Configuration 8-bit timer with 8-bit 8-bit timer with 8-bit 16-bit timer (with input 4-bit counter...
Page 212: 17. Timer Ra
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17. Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler. 17.1 Overview The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6 the Specification of Each Modes).
Page 213: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.2 Registers 17.2.1 Timer RA Control Register (TRACR) Address 0100h Symbol — — TUNDF TEDGF — TSTOP TCSTF TSTART After Reset Symbol Bit Name Function...
Page 214: Timer Ra Mode Register (Tramr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.2.3 Timer RA Mode Register (TRAMR) Address 0102h Symbol TCKCUT TCK2 TCK1 TCK0 — TMOD2 TMOD1 TMOD0 After Reset Symbol Bit Name Function TMOD0 Timer RA operating mode select bit b2 b1 b0...
Page 215: Timer Ra Register (Tra)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.2.5 Timer RA Register (TRA) Address 0104h Symbol — — — — — — — — After Reset (Note 1) Mode Function Setting Range b7 to b0 All modes...
Page 216: Timer Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.3 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode Specifications). Table 17.2 Timer Mode Specifications Item...
Page 217: Timer Write Control During Count Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.3.2 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter.
Page 218: Pulse Output Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.4 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pulse Output Mode Specifications).
Page 219: Timer Ra I/O Control Register (Traioc) In Pulse Output Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.4.1 Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode Address 0101h Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL After Reset Symbol Bit Name...
Page 220: Event Counter Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.5 Event Counter Mode In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 17.4 Event Counter Mode Specifications).
Page 221: Timer Ra I/O Control Register (Traioc) In Event Counter Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.5.1 Timer RA I/O Control Register (TRAIOC) in Event Counter Mode Address 0101h Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL After Reset Symbol Bit Name...
Page 222: Pulse Width Measurement Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.6 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the TRAIO pin is measured (refer to Table 17.5 Pulse Width Measurement Mode Specifications).
Page 223: Timer Ra I/O Control Register (Traioc) In Pulse Width Measurement Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.6.1 Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement Mode Address 0101h Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL After Reset Symbol...
Page 224: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.6.2 Operating Example n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh Count start Underflow Count stop Count stop...
Page 225: Pulse Period Measurement Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.7 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the TRAIO pin is measured (refer to Table 17.6 Pulse Period Measurement Mode Specifications).
Page 226: Timer Ra I/O Control Register (Traioc) In Pulse Period Measurement Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.7.1 Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement Mode Address 0101h Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL After Reset Symbol...
Page 227: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.7.2 Operating Example Underflow signal of timer RA prescaler Set to 1 by program TSTART bit in TRACR register Count start Measurement pulse (TRAIO pin input) TRA reloaded...
Page 228: Notes On Timer Ra
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 17. Timer RA 17.8 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts.
Page 229: 18. Timer Rb
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18. Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler. 18.1 Overview The prescaler and timer each consist of a reload register and counter (refer to Tables 18.2 to 18.5 the Specifications of Each Mode).
Page 230: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.2 Registers 18.2.1 Timer RB Control Register (TRBCR) Address 0108h Symbol — — — — — TSTOP TCSTF TSTART After Reset Symbol Bit Name Function...
Page 231: Timer Rb I/O Control Register (Trbioc)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.2.3 Timer RB I/O Control Register (TRBIOC) Address 010Ah Symbol — — — — INOSEG INOSTG TOCNT TOPL After Reset Symbol Bit Name Function TOPL...
Page 232: Timer Rb Prescaler Register (Trbpre)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.2.5 Timer RB Prescaler Register (TRBPRE) Address 010Ch Symbol — — — — — — — — After Reset Mode Function Setting Range b7 to b0 Timer mode Counts an internal count source or...
Page 233: Timer Rb Primary Register (Trbpr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.2.7 Timer RB Primary Register (TRBPR) Address 010Eh Symbol — — — — — — — — After Reset Mode Function Setting Range b7 to b0 Timer mode Counts timer RB prescaler underflows...
Page 234: Timer Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.3 Timer Mode In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 18.2 Timer Mode Specifications).
Page 235: Timer Write Control During Count Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.3.2 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter.
Page 236 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program.
Page 237: Programmable Waveform Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.4 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 18.3 Programmable Waveform Generation Mode Specifications).
Page 238: Timer Rb I/O Control Register (Trbioc) In Programmable Waveform Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.4.1 Timer RB I/O Control Register (TRBIOC) in Programmable Waveform Generation Mode Address 010Ah Symbol — — — — INOSEG INOSTG TOCNT TOPL After Reset...
Page 239: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.4.2 Operating Example Set to 1 by program TSTART bit in TRBCR register Count source Timer RB prescaler underflow signal Timer RB secondary reloads Timer RB primary reloads Counter of timer RB Set to 0 when interrupt...
Page 240: Programmable One-Shot Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.5 Programmable One-shot Generation Mode In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 18.4 Programmable One-Shot Generation Mode Specifications).
Page 241: Timer Rb I/O Control Register (Trbioc) In Programmable One-Shot Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode Address 010Ah Symbol — — — — INOSEG INOSTG TOCNT TOPL After Reset...
Page 242: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.5.2 Operating Example Set to 1 by program TSTART bit in TRBCR register Set to 0 when Set to 1 by INT0 pin Set to 1 by program counting ends input trigger...
Page 243: One-Shot Trigger Selection
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.5.3 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes: •...
Page 244: Programmable Wait One-Shot Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.6 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 18.5 Programmable Wait One-Shot Generation Mode Specifications).
Page 245: Timer Rb I/O Control Register (Trbioc) In Programmable Wait One-Shot Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode Address 010Ah Symbol — — — — INOSEG INOSTG TOCNT TOPL After Reset...
Page 246: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.6.2 Operating Example Set to 1 by program TSTART bit in TRBCR register Set to 1 by setting 1 to TOSST bit in TRBOCR Set to 0 when register, or INT0 pin input trigger.
Page 247: Notes On Timer Rb
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.7 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts.
Page 248: Programmable One-Shot Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 18. Timer RB 18.7.3 Programmable One-shot Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following points: •...
Page 249: 19. Timer Rc
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19. Timer RC Timer RC is a 16-bit timer with four I/O pins. 19.1 Overview Timer RC uses either f1, fOCO40M or fOCO-F as its operation clock. Table 19.1 lists the Timer RC Operation Clock.
Page 250 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC f1, f2, f4, f8, f32, fOCO40M, fOCO-F TRCMR register TRCCR1 register TRCIER register INT0 Count source TRCSR register TRCCLK select circuit TRCIOR0 register TRCIOA/TRCTRG TRCIOR1 register...
Page 251: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2 Registers Table 19.3 lists the Registers Associated with Timer RC. Table 19.3 Registers Associated with Timer RC Mode Timer Address Symbol Related Information Input...
Page 252: Module Standby Control Register (Mstcr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.1 Module Standby Control Register (MSTCR) Address 0008h Symbol — — MSTTRC MSTTRD MSTIIC — — — After Reset Symbol Bit Name Function —...
Page 253: Timer Rc Control Register 1 (Trccr1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.3 Timer RC Control Register 1 (TRCCR1) Address 0121h Symbol CCLR TCK2 TCK1 TCK0 After Reset Symbol Bit Name Function Function varies according to the operating mode TRCIOA output level select bit (function).
Page 254: Timer Rc Status Register (Trcsr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.5 Timer RC Status Register (TRCSR) Address 0123h Symbol — — — IMFD IMFC IMFB IMFA After Reset Symbol Bit Name Function IMFA Input capture / compare match flag A...
Page 255: Timer Rc I/O Control Register 0 (Trcior0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.6 Timer RC I/O Control Register 0 (TRCIOR0) Address 0124h Symbol — IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 After Reset Symbol Bit Name Function...
Page 256: Timer Rc Counter (Trc)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.8 Timer RC Counter (TRC) Address 0127h to 0126h Symbol — — — — — — — — After Reset Symbol —...
Page 257: Timer Rc Control Register 2 (Trccr2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.10 Timer RC Control Register 2 (TRCCR2) Address 0130h Symbol TCEG1 TCEG0 CSTP — — POLD POLC POLB After Reset Symbol Bit Name Function POLB...
Page 258: Timer Rc Output Master Enable Register (Trcoer)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.12 Timer RC Output Master Enable Register (TRCOER) Address 0132h Symbol — — — After Reset Symbol Bit Name Function 0: Enable output TRCIOA output disable bit 1: Disable output (The TRCIOA pin is used as a programmable I/O port.)
Page 259: Timer Rc Pin Select Register (Trbrcsr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.14 Timer RC Pin Select Register (TRBRCSR) Address 0181h Symbol — — TRCCLKSEL1 TRCCLKSEL0 — — — — After Reset Symbol Bit Name Function —...
Page 260: Timer Rc Pin Select Register 0 (Trcpsr0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.2.15 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Symbol — — — TRCIOBSEL0 — — — TRCIOASEL0 After Reset Symbol Bit Name Function...
Page 261: Common Items For Multiple Modes
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.3 Common Items for Multiple Modes 19.3.1 Count Source The method of selecting the count source is common to all modes. Table 19.5 lists the Count Source Selection, and Figure 19.2 shows a Count Source Block Diagram.
Page 262: Buffer Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.3.2 Buffer Operation Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer register for the TRCGRA or TRCGRB register.
Page 263 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Compare match signal TRCGRC TRCGRA Comparator register register TRC register TRCGRA register Transfer TRCGRC register (buffer) TRCIOA output The above applies under the following conditions: •...
Page 264: Digital Filter
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.3.3 Digital Filter The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined when three matches occur.
Page 265: Forced Cutoff Of Pulse Output
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.3.4 Forced Cutoff of Pulse Output When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a programmable I/O port by means of input to the INT0 pin.
Page 266 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC EA bit EA bit write value INT0 input Timer RC TRCIOA output data Port P1_1 PTO bit output data Port P1_1 input data EB bit EB bit...
Page 267: Timer Mode (Input Capture Function)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.4 Timer Mode (Input Capture Function) This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A, B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj register (input capture).
Page 268 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC fOCO128 fOCO-S or Divided fOCO-F by 128 IOA3 = 0 Input capture signal Edge TRCIOA IOA3 = 1 selection TRCGRA TRC register (Note 1) register TRCGRC...
Page 269: Timer Rc I/O Control Register 0 (Trcior0) For Input Capture Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.4.1 Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Function Address 0124h Symbol — IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 After Reset...
Page 270: Timer Rc I/O Control Register 1 (Trcior1) For Input Capture Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.4.2 Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Function Address 0125h Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 After Reset...
Page 271: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.4.3 Operating Example TRCCLK input count source TRC register count value FFFFh 0009h 0006h 0000h TSTART bit in TRCMR register 65536 TRCIOA input TRCGRA register 0006h...
Page 272: Timer Mode (Output Compare Function)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.5 Timer Mode (Output Compare Function) This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D) match (compare match).
Page 273 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Compare match signal Output TRCIOA control Comparator TRCGRA Compare match signal Output TRCIOC control Comparator TRCGRC Compare match signal Output TRCIOB control Comparator TRCGRB...
Page 274: Timer Rc Control Register 1 (Trccr1) For Output Compare Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.5.1 Timer RC Control Register 1 (TRCCR1) for Output Compare Function Address 0121h Symbol CCLR TCK2 TCK1 TCK0 After Reset Symbol Bit Name Function 0: Initial output “L”...
Page 275: Timer Rc I/O Control Register 0 (Trcior0) For Output Compare Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.5.2 Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function Address 0124h Symbol — IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 After Reset...
Page 276: Timer Rc I/O Control Register 1 (Trcior1) For Output Compare Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.5.3 Timer RC I/O Control Register 1 (TRCIOR1) for Output Compare Function Address 0125h Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 After Reset...
Page 277: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.5.4 Operating Example Count source TRC register value Count restarts Count stops TSTART bit in TRCMR register Output level held TRCIOA output Output inverted at compare match Initial output “L”...
Page 278: Changing Output Pins In Registers Trcgrc And Trcgrd
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.5.5 Changing Output Pins in Registers TRCGRC and TRCGRD The TRCGRC register can be used for output control of the TRCIOA pin, and the TRCGRD register can be used for output control of the TRCIOB pin.
Page 279 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Count source Value in TRC register FFFFh 0000h Initial output “L” TRCIOA output Output inverted by compare match IMFA bit in TRCSR register Set to 0 by a program Set to 0 by a program...
Page 280: Pwm Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.6 PWM Mode This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output. The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.) Table 19.11 lists the Specifications of PWM Mode, Figure 19.13 shows a PWM Mode Block Diagram, Table 19.12 lists the Functions of TRCGRj Register in PWM Mode, and Figures 19.14 and 19.15 show Operating Examples of...
Page 281 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Compare match signal Comparator TRCGRA TRCIOB Compare match signal (Note 1) Comparator TRCGRB TRCIOC Output Compare match signal control Comparator TRCGRC TRCIOD (Note 2) Compare match signal...
Page 282: Timer Rc Control Register 1 (Trccr1) In Pwm Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode Address 0121h Symbol CCLR TCK2 TCK1 TCK0 After Reset Symbol Bit Name Function Disabled in PWM mode TRCIOA output level select bit...
Page 283 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Table 19.12 Functions of TRCGRj Register in PWM Mode Register Setting Register Function PWM Output Pin − − TRCGRA General register. Set the PWM period. −...
Page 284: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.6.3 Operating Example Count source Value in TRC register Active level “H” Initial output “L” Inactive level “L” TRCIOB output to compare match TRCIOC output Initial output “H”...
Page 285 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC TRC register value 0000h TSTART bit in TRCIOB output does not switch to “L” because TRCMR register no compare match with the TRCGRB register has occurred Duty 0% TRCIOB output...
Page 286: Pwm2 Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.7 PWM2 Mode This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the pin output switches to active level.
Page 287 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Table 19.13 Specifications of PWM2 Mode Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge) input to TRCCLK pin Count operation Increment TRC register PWM waveform...
Page 288: Timer Rc Control Register 1 (Trccr1) In Pwm2 Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode Address 0121h Symbol CCLR TCK2 TCK1 TCK0 After Reset Symbol Bit Name Function Disabled in PWM2 mode TRCIOA output level select bit...
Page 289: Timer Rc Control Register 2 (Trccr2) In Pwm2 Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode Address 0130h Symbol TCEG1 TCEG0 CSTP — — POLD POLC POLB After Reset Symbol Bit Name...
Page 290 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Table 19.14 Functions of TRCGRj Register in PWM2 Mode Register Setting Register Function PWM2 Output Pin − TRCGRA General register. Set the PWM period. TRCIOB pin −...
Page 291: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.7.4 Operating Example Count source TRC register value FFFFh TRC register cleared at TRCGRA register compare match Previous value held if the Set to 0000h by a program TSTART bit is set to 0...
Page 292 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC Count source TRC register value TRC register cleared at TRCGRA register FFFFh compare match TRC register (counter) cleared at TRCTRG pin trigger input Previous value held if the...
Page 293 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC • TRCGRB register setting value greater than TRCGRA • TRCGRC register setting value greater than TRCGRA register setting value register setting value TRC register value TRC register value 0000h...
Page 294: Timer Rc Interrupt
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.8 Timer RC Interrupt Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector.
Page 295: Notes On Timer Rc
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC 19.9 Notes on Timer RC 19.9.1 TRC Register • The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at compare match with TRCGRA register).
Page 296: Input Capture Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 19. Timer RC • After switching the count source from fOCO-F to fOCO40M, allow a minimum of two cycles of fOCO-F to elapse after changing the clock setting before stopping fOCO-F. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops).
Page 297: 20. Timer Re
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20. Timer RE Timer RE has the 4-bit counter and 8-bit counter. 20.1 Overview Timer RE has the following 2 modes: •...
Page 298: Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2 Real-Time Clock Mode In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week.
Page 299 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE Table 20.1 Real-Time Clock Mode Specifications Item Specification Count source Count operation Increment Count start condition 1 (count starts) is written to TSTART bit in TRECR1 register Count stop condition 0 (count stops) is written to TSTART bit in TRECR1 register Interrupt request generation...
Page 300: Timer Re Second Data Register (Tresec) In Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2.1 Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode Address 0118h Symbol SC12 SC11 SC10 SC03 SC02 SC01 SC00 After Reset Symbol Bit Name...
Page 301: Timer Re Hour Data Register (Trehr) In Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2.3 Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode Address 011Ah Symbol — HR11 HR10 HR03 HR02 HR01 HR00 After Reset Symbol Bit Name...
Page 302: Timer Re Control Register 1 (Trecr1) In Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2.5 Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode Address 011Ch Symbol TSTART H12_H24 TRERST — TCSTF — After Reset Symbol Bit Name Function...
Page 303: Timer Re Control Register 2 (Trecr2) In Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2.6 Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode Address 011Dh Symbol — — COMIE WKIE DYIE HRIE MNIE SEIE After Reset Symbol...
Page 304: Timer Re Count Source Select Register (Trecsr) In Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2.7 Timer RE Count Source Select Register (TRECSR) in Real-Time Clock Mode Address 011Eh Symbol — — — — RCS3 RCS2 RCS1 RCS0 After Reset...
Page 305: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.2.8 Operating Example Approx. Approx. 62.5 ms 62.5 ms BSY bit Bits SC12 to SC00 in TRESEC register Bits MN12 to MN00 in TREMIN register Bits HR11 to HR00 in (Not changed)
Page 306: Output Compare Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.3 Output Compare Mode In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit counter.
Page 307 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE Table 20.3 Output Compare Mode Specifications Item Specification Count sources f4, f8, f32, fC4 Count operations • Increment • When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues.
Page 308: Timer Re Counter Data Register (Tresec) In Output Compare Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.3.1 Timer RE Counter Data Register (TRESEC) in Output Compare Mode Address 0118h Symbol — — — — — — — —...
Page 309: Timer Re Control Register 1 (Trecr1) In Output Compare Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.3.3 Timer RE Control Register 1 (TRECR1) in Output Compare Mode Address 011Ch Symbol TSTART H12_H24 TRERST — TCSTF — After Reset Symbol Bit Name Function...
Page 310: Timer Re Count Source Select Register (Trecsr) In Output Compare Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.3.5 Timer RE Count Source Select Register (TRECSR) in Output Compare Mode Address 011Eh Symbol — — — — RCS3 RCS2 RCS1 RCS0 After Reset...
Page 311: Operating Example
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.3.6 Operating Example Count starts Matched Matched Matched TREMIN register setting value Time 1 by a program Set to TSTART bit in TRECR1 register 2 cycles of maximum count source TCSTF bit in...
Page 312: Notes On Timer Re
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.4 Notes on Timer RE 20.4.1 Starting and Stopping Count Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop.
Page 313 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE TSTART in TRECR1 = 0 Stop timer RE operation TCSTF in TRECR1 = 0? TREIC ← 00h (disable timer RE interrupt) TRERST in TRECR1 = 1 Timer RE register and control circuit reset...
Page 314: Time Reading Procedure Of Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 20. Timer RE 20.4.3 Time Reading Procedure of Real-Time Clock Mode In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Page 315: Serial Interface (Uart0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21. Serial Interface (UART0) The serial interface consists of two channels, UART0, UART2. This chapter describes the UART0. 21.1 Overview UART0 has a dedicated timer to generate a transfer clock and operate independently.
Page 316 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) Clock synchronous type PRYE = 0 Clock UART (7 bits) disabled synchronous UART (7 bits) UART0 receive register UART (8 bits) type RXD0 PAR enabled...
Page 317: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.2 Registers 21.2.1 UART0 Transmit/Receive Mode Register (U0MR) Address 00A0h (U0MR) Symbol — PRYE STPS CKDIR SMD2 SMD1 SMD0 After Reset Symbol Bit Name Function...
Page 318: Uart0 Transmit Buffer Register (U0Tb)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.2.3 UART0 Transmit Buffer Register (U0TB) Address 00A3h to 00A2h (U0TB) Symbol — — — — — — — — After Reset Symbol —...
Page 319: Uart0 Transmit/Receive Control Register 0 (U0C0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.2.4 UART0 Transmit/Receive Control Register 0 (U0C0) Address 00A4h (U0C0) Symbol UFORM CKPOL — TXEPT — CLK1 CLK0 After Reset Symbol Bit Name Function...
Page 320: Uart0 Receive Buffer Register (U0Rb)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.2.6 UART0 Receive Buffer Register (U0RB) Address 00A7h to 00A6h (U0RB) Symbol — — — — — — — — After Reset Symbol —...
Page 321: Uart0 Pin Select Register (U0Sr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.2.7 UART0 Pin Select Register (U0SR) Address 0188h Symbol — — — CLK0SEL0 — RXD0SEL0 — TXD0SEL0 After Reset Symbol Bit Name Function TXD0SEL0 TXD0 pin select bit...
Page 322: Clock Synchronous Serial I/O Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.3 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 21.2 lists the Clock Synchronous Serial I/O Mode Specifications.
Page 323 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) Table 21.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Function U0TB b0 to b7 Set data transmission. U0RB b0 to b7 Receive data can be read.
Page 324 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) Table 21.4 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. After UART0 operating mode is selected, the TXD0 pin outputs a “H” level until transfer starts. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 21.4 I/O Pin Functions in Clock Synchronous Serial I/O Mode...
Page 325 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) • Transmit Timing Example (Internal Clock Selected) Transfer clock TE bit in U0C1 register Data is set in U0TB register. TI bit in U0C1 register Data transfer from U0TB register to UART0 transmit register...
Page 326: Polarity Select Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.3.1 Polarity Select Function Figure 21.4 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity.
Page 327: Continuous Receive Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.3.3 Continuous Receive Mode Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (continuous receive mode enabled).
Page 328: Clock Asynchronous Serial I/O (Uart) Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.4 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format. Table 21.5 lists the UART Mode Specifications.
Page 329 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) Table 21.6 Registers Used and Settings in UART Mode Register Function U0TB b0 to b8 Set transmit data. U0RB b0 to b8 Receive data can be read.
Page 330 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) Table 21.7 lists the I/O Pin Functions in UART Mode. After the UART0 operating mode is selected, the TXD0 pin outputs a “H” level until transfer starts. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 21.7 I/O Pin Functions in UART Mode...
Page 331 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) • Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) Transfer clock TE bit in U0C1 register Data is set in U0TB register.
Page 332 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) • Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit) U0BRG output RE bit in U0C1 register Stop bit Start bit...
Page 333: Bit Rate
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.4.1 Bit Rate In UART mode, the bit rate is the frequency divided by the U0BRG register and divided by 16. UART mode •...
Page 334: Notes On Serial Interface (Uart0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 21. Serial Interface (UART0) 21.5 Notes on Serial Interface (UART0) • When reading data from the U0RB register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units.
Page 335: Serial Interface (Uart2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22. Serial Interface (UART2) The serial interface consists of three channels, UART0 to UART2. This chapter describes the UART2. 22.1 Overview UART2 has a dedicated timer to generate a transfer clock and operate independently.
Page 336 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Not inverted RXD2 IOPOL = 0 RXD data inversion circuit IOPOL = 1 Inverted Clock synchronous type UART (7 bits) UART (8 bits) Clock...
Page 337: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2 Registers 22.2.1 UART2 Transmit/Receive Mode Register (U2MR) Address 00A8h Symbol IOPOL PRYE STPS CKDIR SMD2 SMD1 SMD0 After Reset Symbol Bit Name Function...
Page 338: Uart2 Transmit Buffer Register (U2Tb)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.3 UART2 Transmit Buffer Register (U2TB) Address 00ABh to 00AAh Symbol — — — — — — — — After Reset Symbol —...
Page 339: Uart2 Transmit/Receive Control Register 0 (U2C0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.4 UART2 Transmit/Receive Control Register 0 (U2C0) Address 00ACh Symbol UFORM CKPOL TXEPT CLK1 CLK0 After Reset Symbol Bit Name Function CLK0 U2BRG count source...
Page 340: Uart2 Transmit/Receive Control Register 1 (U2C1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.5 UART2 Transmit/Receive Control Register 1 (U2C1) Address 00ADh Symbol U2ERE U2LCH U2RRM U2IRS After Reset Symbol Bit Name Function Transmit enable bit 0: Transmission disabled 1: Transmission enabled...
Page 341: Uart2 Receive Buffer Register (U2Rb)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.6 UART2 Receive Buffer Register (U2RB) Address 00AFh to 00AEh Symbol — — — — — — — — After Reset Symbol —...
Page 342: Uart2 Digital Filter Function Select Register (Urxdf)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.7 UART2 Digital Filter Function Select Register (URXDF) Address 00B0h Symbol — — — — — DF2EN — — After Reset Symbol Bit Name Function...
Page 343: Uart2 Special Mode Register 4 (U2Smr4)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.9 UART2 Special Mode Register 4 (U2SMR4) Address 00BCh Symbol SWC9 SCLHI ACKC ACKD STSPSEL STPREQ RSTAREQ STAREQ After Reset Symbol Bit Name Function...
Page 344: Uart2 Special Mode Register 2 (U2Smr2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.11 UART2 Special Mode Register 2 (U2SMR2) Address 00BEh Symbol — SDHI SWC2 STAC IICM2 After Reset Symbol Bit Name Function IICM2 C mode select bit 2...
Page 345: Uart2 Pin Select Register 0 (U2Sr0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.2.13 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Symbol — — RXD2SEL1 RXD2SEL0 — — TXD2SEL1 TXD2SEL0 After Reset Symbol Bit Name Function...
Page 346: Clock Synchronous Serial I/O Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.3 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 22.2 lists the Clock Synchronous Serial I/O Mode Specifications.
Page 347 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register Function b0 to b7 Set transmit data. U2TB b0 to b7 Receive data can be read.
Page 348 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.4 lists the Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output Pin Function Not Selected). Note that for a period from when UART2 operating mode is selected to when transfer starts, the TXD2 pin outputs a “H”...
Page 349 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) (1) Transmit Timing Example (Internal Clock Selected) Transfer clock TE bit in U2C1 register Data is set in U2TB register. TI bit in U2C1 register Data transfer from U2TB register to UART2 transmit register...
Page 350: Measure For Dealing With Communication Errors
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.3.1 Measure for Dealing with Communication Errors If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below: •...
Page 351: Lsb First/Msb First Select Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.3.3 LSB First/MSB First Select Function Use the UFORM bit in the U2C0 register to select the transfer format. Figure 22.5 shows the Transfer Format. (1) UFORM Bit in U2C0 Register = 0 (LSB first) CLK2 TXD2...
Page 352: Serial Data Logic Switching Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.3.5 Serial Data Logic Switching Function If the U2LCH bit in the U2C1 register is set to 1 (inverted), the data written to the U2TB register has its logic inverted before being transmitted.
Page 353: Clock Asynchronous Serial I/O (Uart) Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.4 Clock Asynchronous Serial I/O (UART) Mode In UART mode, data is transmitted and received after setting the desired bit rate and transfer data format. Table 22.5 lists the UART Mode Specifications.
Page 354 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.6 Registers Used and Settings in UART Mode Register Function U2TB b0 to b8 Set transmit data. U2RB b0 to b8 (1, 2) Receive data can be read.
Page 355 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.7 lists the I/O Pin Functions in UART Mode. Note that for a period from when the UART2 operating mode is selected to when transfer starts, the TXD2 pin outputs “H”.
Page 356 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) (1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) The transfer clock stops once because “H” is applied to CTS pin when the stop bit is verified. The transfer clock resumes running immediately after “L”...
Page 357: Bit Rate
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Receive Timing Example When Transfer Data 8 Bits is Long (Parity Disabled, One Stop Bit) U2BRG count source RE bit in U2C1 register Stop bit Start bit...
Page 358: Measure For Dealing With Communication Errors
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.4.2 Measure for Dealing with Communication Errors If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below: •...
Page 359: Serial Data Logic Switching Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.4.4 Serial Data Logic Switching Function The data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received data has its logic inverted when read from the U2RB register.
Page 360: Cts/Rts Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.4.6 CTS/RTS Function The CTS function is used to start transmit operation when “L” is applied to the CTS2/RTS2 pin. Transmit operation begins when the CTS2/RTS2 pin is held low.
Page 361: Special Mode 1 (I 2 C Mode)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.5 Special Mode 1 (I C Mode) C mode is provided for use as a simplified I C interface compatible mode. Table 22.9 lists the I C Mode Specifications.
Page 362 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) SDA2 Start/stop condition generation block STSPSEL = 1 DTC request SDA (STSP) Delay (source number 15) SCL (STSP) circuit STSPSEL = 0 IICM2 = 1 UART2 transmit/NACK Transmit...
Page 363 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.10 Registers Used and Settings in I C Mode (1) Function Register Master Slave b0 to b7 Set transmit data. Set transmit data.
Page 364 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.11 Registers Used and Settings in I C Mode (2) Function Register Master Slave U2SMR3 b0, b2, b4, and Set to 0.
Page 365 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.12 C Mode Functions C Mode (SMD2 to SMD0 = 010b, IICM = 1) Clock Synchronous Serial I/O Mode IICM2 = 0 (NACK/ACK interrupt) IICM2 = 1 (UART transmit/receive interrupt) Function...
Page 366 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit...
Page 367: Detection Of Start And Stop Conditions
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.5.1 Detection of Start and Stop Conditions Whether a start or a stop condition has been detected is determined. A start condition detect interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state.
Page 368: Output Of Start And Stop Conditions
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.5.2 Output of Start and Stop Conditions A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start). A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start).
Page 369: Arbitration
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.5.3 Arbitration Unmatching of the transmit data and SDA2 pin input data is checked in synchronization with the rising edge of SCL2.
Page 370: Sda Input
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.5.6 SDA Input When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the U2RB register.
Page 371: Multiprocessor Communication Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.6 Multiprocessor Communication Function When the multiprocessor communication function is used, data transmission/reception can be performed between a number of processors sharing communication lines by asynchronous serial communication, in which a multiprocessor bit is added to the data.
Page 372 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Reception Clock synchronous type UART (7 bits) PRYE = 0 Clock UART UART (8 bits) synchronous (7 bits) UART2 receive register disabled type DF2EN = 0...
Page 373 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Table 22.14 Registers and Settings in Multiprocessor Communication Function Register Function b0 to b7 Set transmit data. U2TB MPTB Set to 0 or 1. b0 to b7 Receive data can be read.
Page 374: Multiprocessor Transmission
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.6.1 Multiprocessor Transmission Figure 22.19 shows a Sample Flowchart of Multiprocessor Data Transmission. Set the MPBT bit in the U2TB register to 1 for ID transmission cycles.
Page 375: Multiprocessor Reception
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.6.2 Multiprocessor Reception Figure 22.20 shows a Sample Flowchart of Multiprocessor Data Reception. When the MPIE bit in the U2SMR5 register is set to 1, communication data is ignored until data in which the multiprocessor bit is 1 is received.
Page 376 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) Start Receive Stop Receive Marked state data (ID1) MPRB data (DATA1) MPRB (Idle state) Serial data 1 frame 1 frame MP bit in U2SMR5 register MPIE bit in...
Page 377: Rxd2 Digital Filter Select Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.6.3 RXD2 Digital Filter Select Function When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is loaded internally via the digital filter circuit for noise reduction.
Page 378: Notes On Serial Interface (Uart2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.7 Notes on Serial Interface (UART2) 22.7.1 Clock Synchronous Serial I/O Mode 22.7.1.1 Transmission/Reception When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is ready for a receive operation.
Page 379: Clock Asynchronous Serial I/O (Uart) Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 22. Serial Interface (UART2) 22.7.2 Clock Asynchronous Serial I/O (UART) Mode 22.7.2.1 Transmission/Reception When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is ready for a receive operation.
Page 380: 23. Clock Synchronous Serial Interface
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 23. Clock Synchronous Serial Interface 23. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock synchronous serial interface Synchronous serial communication unit (SSU) Clock synchronous communication mode 4-wire bus communication mode C bus Interface...
Page 381: Synchronous Serial Communication Unit (Ssu)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24. Synchronous Serial Communication Unit (SSU) Synchronous serial communication unit (SSU) supports clock synchronous serial data communication. 24.1 Overview Table 24.1 lists a Synchronous Serial Communication Unit Specifications, Figure 24.1 shows a Block Diagram of Synchronous Serial Communication Unit and Table 24.2 lists the Pin Configuration of Synchronous Serial...
Page 382 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) Internal clock (f1/i) Internal clock generation circuit Multiplexer SSCK SSMR register SSCRL register SSCRH register Transmit/receive SSER register control circuit SSSR register SSMR2 register...
Page 383: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2 Registers 24.2.1 Module Standby Control Register (MSTCR) Address 0008h Symbol — — MSTTRC MSTTRD MSTIIC — — —...
Page 384: Ss Bit Counter Register (Ssbr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.3 SS Bit Counter Register (SSBR) Address 0193h Symbol — — — — After Reset Symbol Bit Name Function b3 b2 b1 b0 SSU data transfer length set bit...
Page 385: Ss Receive Data Register (Ssrdr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.5 SS Receive Data Register (SSRDR) Address 0197h to 0196h Symbol — — — — — — — —...
Page 386: Ss Control Register L (Sscrl)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.7 SS Control Register L (SSCRL) Address 0199h Symbol — — SOLP — — SRES — After Reset Symbol Bit Name Function...
Page 387: Ss Mode Register (Ssmr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.8 SS Mode Register (SSMR) Address 019Ah Symbol CPOS CPHS — After Reset Symbol Bit Name Function Bits counter 3 to 0 b3 b2 b1 b0 0 0 0 0: 16 bits left 0 0 0 1: 1 bit left...
Page 388: Ss Enable Register (Sser)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.9 SS Enable Register (SSER) Address 019Bh Symbol TEIE — — CEIE After Reset Symbol Bit Name Function CEIE Conflict error interrupt enable bit 0: Disables conflict error interrupt request...
Page 389: Ss Status Register (Sssr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.10 SS Status Register (SSSR) Address 019Ch Symbol TDRE TEND RDRF — — ORER — After Reset Symbol Bit Name Function 0: No conflict errors generated...
Page 390: Ss Mode Register 2 (Ssmr2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.2.11 SS Mode Register 2 (SSMR2) Address 019Dh Symbol BIDE SCKS CSS1 CSS0 SCKOS SOOS CSOS SSUMS After Reset Symbol Bit Name Function...
Page 391: Common Items For Multiple Modes
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.3 Common Items for Multiple Modes 24.3.1 Transfer Clock The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4) and an external clock.
Page 392 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) • SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge), and CPOS bit = 0 (“H” when clock stops) SSCK SSO, SSI •...
Page 393: Ss Shift Register (Sstrsr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.3.2 SS Shift Register (SSTRSR) The SSTRSR register is a shift register for transmitting and receiving serial data. When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register.
Page 394: Interrupt Requests
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.3.3 Interrupt Requests Synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial communication unit interrupt vector table, determining interrupt sources by flags is required.
Page 395: Communication Modes And Pin Functions
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.3.4 Communication Modes and Pin Functions Synchronous serial communication unit switches the functions of the I/O pins in each communication mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Page 396: Clock Synchronous Communication Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.4 Clock Synchronous Communication Mode 24.4.1 Initialization in Clock Synchronous Communication Mode Figure 24.4 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or reception.
Page 397: Data Transmission
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.4.2 Data Transmission Figure 24.5 shows an Example of Synchronous Serial Communication Unit Operation for Data Transmission (Clock Synchronous Communication Mode). During data transmission, the synchronous serial communication unit operates as described below.
Page 398 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) Start Initialization (1) After reading the SSSR register and confirming Read TDRE bit in SSSR register that the TDRE bit is set to 1, write the transmit data to the SSTDR register.
Page 399: Data Reception
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.4.3 Data Reception Figure 24.7 shows an Example of Synchronous Serial Communication Unit Operation for Data Reception (Clock Synchronous Communication Mode). During data reception, synchronous serial communication unit operates as described below.
Page 400 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) Start Initialization (1) After setting each register in the synchronous serial Dummy read of SSRDR register communication unit register, a dummy read of the SSRDR register is performed and the receive operation is started.
Page 401: Data Transmission/Reception
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.4.3.1 Data Transmission/Reception Data transmission/reception is an operation combining data transmission and reception which were described earlier. Transmission/reception is started by writing data to the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
Page 402 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) Start Initialization (1) After reading the SSSR register and confirming Read TDRE bit in SSSR register that the TDRE bit is set to 1, write the transmit data to the SSTDR register.
Page 403: Operation In 4-Wire Bus Communication Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.5 Operation in 4-Wire Bus Communication Mode In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication.
Page 404: Initialization In 4-Wire Bus Communication Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.5.1 Initialization in 4-Wire Bus Communication Mode Figure 24.10 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0 (receive disabled), and initialize the synchronous serial communication unit.
Page 405: Data Transmission
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.5.2 Data Transmission Figure 24.11 shows an Example of Synchronous Serial Communication Unit Operation during Data Transmission (4-Wire Bus Communication Mode). During the data transmit operation, synchronous serial communication unit operates as described below.
Page 406 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) • CPHS bit = 0 (data change at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) High-impedance (output)
Page 407: Data Reception
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.5.3 Data Reception Figure 24.12 shows an Example of Synchronous Serial Communication Unit Operation during Data Reception (4-Wire Bus Communication Mode). During data reception, synchronous serial communication unit operates as described below.
Page 408 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) • CPHS bit = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits) High-impedance (output)
Page 409: Scs Pin Control And Arbitration
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.5.4 SCS Pin Control and Arbitration When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as the master device) and check the arbitration of the SCS pin before starting serial transfer.
Page 410: Notes On Synchronous Serial Communication Unit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 24. Synchronous Serial Communication Unit (SSU) 24.6 Notes on Synchronous Serial Communication Unit Set the IICSEL bit in the SSUIICSR register to 0 (select SSU function) to use the synchronous serial communication unit function.
Page 411: I 2 C Bus Interface
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25. I C bus Interface The I C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips C bus.
Page 412 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Transfer clock generation circuit Output ICCR1 register control Transmit/receive ICCR2 register control circuit Noise ICMR register canceller ICDRT register SAR register Output control...
Page 413 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface SCL input SCL output SDA input SDA output (Master) SCL input SCL input SCL output SCL output SDA input SDA input SDA output SDA output...
Page 414: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2 Registers 25.2.1 Module Standby Control Register (MSTCR) Address 0008h Symbol — — MSTTRC MSTTRD MSTIIC — — — After Reset Symbol Bit Name...
Page 415: Iic Bus Transmit Data Register (Icdrt)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.3 IIC bus Transmit Data Register (ICDRT) Address 0194h Symbol — — — — — — — — After Reset Function b7 to b0 This register stores transmit data.
Page 416: Iic Bus Control Register 1 (Iccr1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.5 IIC bus Control Register 1 (ICCR1) Address 0198h Symbol RCVD CKS3 CKS2 CKS1 CKS0 After Reset Symbol Bit Name Function CKS0 b3 b2 b1 b0...
Page 417: Iic Bus Control Register 2 (Iccr2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.6 IIC bus Control Register 2 (ICCR2) Address 0199h Symbol BBSY SDAO SDAOP SCLO — IICRST — After Reset Symbol Bit Name Function...
Page 418: Iic Bus Mode Register (Icmr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.7 IIC bus Mode Register (ICMR) Address 019Ah Symbol WAIT — — BCWP After Reset Symbol Bit Name Function Bit counters 2 to 0 C bus format (Read: Number of remaining transfer bits;...
Page 419: Iic Bus Interrupt Enable Register (Icier)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.8 IIC bus Interrupt Enable Register (ICIER) Address 019Bh Symbol TEIE NAKIE STIE ACKE ACKBR ACKBT After Reset Symbol Bit Name Function ACKBT Transmit acknowledge...
Page 420: Iic Bus Status Register (Icsr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.9 IIC bus Status Register (ICSR) Address 019Ch Symbol TDRE TEND RDRF NACKF STOP After Reset Symbol Bit Name Function General call address This flag is set to 1 when a general call address is...
Page 421: Slave Address Register (Sar)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.2.10 Slave Address Register (SAR) Address 019Dh Symbol SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 After Reset Symbol Bit Name Function Format select bit 0: I...
Page 422: Common Items For Multiple Modes
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.3 Common Items for Multiple Modes 25.3.1 Transfer Clock When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin.
Page 423: Interrupt Requests
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.3.2 Interrupt Requests The I C bus interface has six interrupt requests when the I C bus format is used and four interrupt requests when the clock synchronous serial format is used.
Page 424: I 2 C Bus Interface Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.4 C bus Interface Mode 25.4.1 C bus Format When the FS bit in the SAR register is set to 0, the I C bus format is used for communication.
Page 425: Master Transmit Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal.
Page 426 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface (master output) (master output) Slave address (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRT register Address + R/W Data 1 Data 2...
Page 427: Master Receive Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal.
Page 428 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Master transmit mode Master receive mode (master output) (master output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register...
Page 429 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface (master output) (master output) (slave output) RDRF bit in ICSR register RCVD bit in ICCR1 register Data n-1 ICDRS register Data n Data n-1 Data n...
Page 430: Slave Transmit Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal.
Page 431 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Slave receive mode Slave transmit mode (master output) (master output) (slave output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in...
Page 432 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Slave receive mode Slave transmit mode (master output) (master output) (slave output) (slave output) TDRE bit in ICSR register TEND bit in ICSR register TRS bit in...
Page 433: Slave Receive Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal.
Page 434 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface (master output) (master output) (slave output) (slave output) RDRF bit in ICSR register ICDRS register Data 1 Data 2 ICDRR register Data 1 Program processing...
Page 435: Clock Synchronous Serial Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.5 Clock Synchronous Serial Mode 25.5.1 Clock Synchronous Serial Format When the FS bit in the SAR register is set to 1, the clock synchronous serial format is used for communication. Figure 25.12 shows the Transfer Format of Clock Synchronous Serial Format.
Page 436: Transmit Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.5.2 Transmit Operation In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the transfer clock.
Page 437: Receive Operation
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.5.3 Receive Operation In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Page 438: Examples Of Register Setting
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.6 Examples of Register Setting Figures 25.15 to 25.18 show Examples of Register Setting When Using I C bus interface. Start •...
Page 439 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Master receive mode TEND bit ← 0 (1) Set the TEND bit to 0 and set to master receive mode. ICSR register (1,2) Set the TDRE bit to 0.
Page 440 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Slave transmit mode (1) Set the AAS bit to 0. AAS bit ← 0 ICSR register (2) Set the transmit data (except the last byte). Write transmit data to ICDRT register (3) Wait until the ICRDT register is empty.
Page 441 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface Slave receive mode (1) Set the AAS bit to 0. AAS bit ← 0 ICSR register (2) Set the ACKBT bit to the transmit device. ICIER register ACKBT bit ←...
Page 442: Noise Canceller
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.7 Noise Canceller The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure 25.19 shows a Noise Canceller Block Diagram.
Page 443: Bit Synchronization Circuit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.8 Bit Synchronization Circuit When the I C bus interface is set to master mode, the high-level period may become shorter if: •...
Page 444: Notes On I 2 C Bus Interface
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 25. I C bus Interface 25.9 Notes on I C bus Interface To use the I C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I C bus interface function selected).
Page 445: 26. Hardware Lin
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0. 26.1 Overview The hardware LIN has the features listed below. Figure 26.1 shows a Hardware LIN Block Diagram.
Page 446: Input/Output Pins
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.2 Input/Output Pins The pin configuration for the hardware LIN is listed in Table 26.1. Table 26.1 Hardware LIN Pin Configuration Name Pin Name Assigned Pin...
Page 447: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.3 Registers The hardware LIN contains the following registers: • LIN Control Register 2 (LINCR2) • LIN Control Register (LINCR) • LIN Status Register (LINST) 26.3.1 LIN Control Register 2 (LINCR2)
Page 448: Lin Control Register (Lincr)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.3.2 LIN Control Register (LINCR) Address 0106h Symbol LINE LSTART RXDSF BCIE SBIE SFIE After Reset Symbol Bit Name Function SFIE Synch Field measurement-completed 0: Synch Field measurement-completed interrupt interrupt enable bit...
Page 449: Function Description
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.4 Function Description 26.4.1 Master Mode Figure 26.2 shows an Operating Example during Header Field Transmission in master mode. Figures 26.3 and 26.4 show Examples of Header Field Transmission Flowchart.
Page 450 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN Timer RA Set to timer mode Bits TMOD2 to TMOD0 in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ←...
Page 451 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN A Synch Break for timer RA is Timer RA Set the timer to start counting generated. TSTART bit in TRACR register ← 1 After writing 1 to the TSTART bit, if registers TRAPRE and TRA for timer RA are not read or the register...
Page 452: Slave Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.4.2 Slave Mode Figure 26.5 shows an Operating Example during Header Field Reception in slave mode. Figure 26.6 through Figure 26.8 show examples of Header Field Reception Flowchart. During header field reception, the hardware LIN operates as follows: (1) When 1 is written to the LSTART bit in the LINCR register for the hardware LIN, Synch Break detection is enabled.
Page 453 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN Timer RA Set to pulse width measurement mode Bits TMOD2 to TMOD0 in TRAMR register ← 011b Timer RA Set the pulse width measurement level to low TEDGSEL bit in TRAIOC register ←...
Page 454 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ←...
Page 455 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN A Synch Field for the hardware LIN is measured. A timer RA interrupt can be used. (The SBDCT flag is set when Hardware LIN Read the Synch Field measurement- the timer RA counter underflows.)
Page 456: Bus Collision Detection Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.4.3 Bus Collision Detection Function The bus collision detection function can be used if UART0 is enabled for transmission (TE bit in U0C1 register = 1).
Page 457: Hardware Lin End Processing
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.4.4 Hardware LIN End Processing Figure 26.10 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing: •...
Page 458: Interrupt Requests
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.5 Interrupt Requests There are four interrupt requests generated by the hardware LIN: Synch Break detection, Completion of Synch Break generation, Completion of Synch Field measurement, and bus collision detection. These interrupts are shared with timer RA.
Page 459: Notes On Hardware Lin
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 26. Hardware LIN 26.6 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point.
Page 460: 27. A/D Converter
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares pins and P1_0 to P1_3. 27.1 Overview Table 27.1 lists the A/D Converter Performance.
Page 461: Block Diagram Of A/D Converter
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter CKS2 = 1 CKS1 to CKS0 fOCO-F = 00b = 01b φAD = 10b CKS2 = 0 = 11b VREF Analog circuit ADSTBY = 0 ADSTBY = 1 AVSS...
Page 462: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.2 Registers 27.2.1 On-Chip Reference Voltage Control Register (OCVREFCR) Address 0026h Symbol — — — — — — — OCVREFAN After Reset Symbol Bit Name Function...
Page 463: A/D Register I (Adi) (I = 0 To 7)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.2.2 A/D Register i (ADi) (i = 0 to 7) Address 00C1h to 00C0h (AD0), 00C3h to 00C2h (AD1), 00C5h to 00C4h (AD2), 00C7h to 00C6h (AD3), 00C9h to 00C8h (AD4), 00CBh to 00CAh (AD5), 00CDh to 00CCh (AD6), 00CFh to 00CEh (AD7) Symbol...
Page 464: A/D Mode Register (Admod)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.2.3 A/D Mode Register (ADMOD) Address 00D4h Symbol ADCAP1 ADCAP0 CKS2 CKS1 CKS0 After Reset Symbol Bit Name Function CKS0 Division select bit b1 b0 0 0: fAD divided by 8 CKS1...
Page 465: A/D Input Select Register (Adinsel)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.2.4 A/D Input Select Register (ADINSEL) Address 00D5h Symbol ADGSEL1 ADGSEL0 — SCAN0 — After Reset Symbol Bit Name Function Analog input pin select bit Refer to Table 27.2 Analog Input Pin Selection —...
Page 466: A/D Control Register 0 (Adcon0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.2.5 A/D Control Register 0 (ADCON0) Address 00D6h Symbol — — — — — — — ADST After Reset Symbol Bit Name Function ADST A/D conversion start flag...
Page 467: A/D Control Register 1 (Adcon1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.2.6 A/D Control Register 1 (ADCON1) Address 00D7h Symbol ADDDAEL ADDDAEN ADSTBY BITS — — — ADEX0 After Reset Symbol Bit Name Function ADEX0 0: Extended analog input pin not selected...
Page 468: Common Items For Multiple Modes
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.3 Common Items for Multiple Modes 27.3.1 Input/Output Pins The analog input shares pins P1_0 to P1_3 in AN8 to AN11. When using the ANi (i = 8 to 11) pin as input, set the corresponding port direction bit to 0 (input mode).
Page 469 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter Table 27.3 shows the Number of Cycles for A/D Conversion Items. The A/D conversion time is defined as follows. The start process time varies depending on which φAD is selected. When 1 (A/D conversion starts) is written to the ADST bit in the ADCON0 register, an A/D conversion starts after the start process time has elapsed.
Page 470: A/D Conversion Start Condition
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.3.3 A/D Conversion Start Condition A software trigger, trigger from timer RC, and external trigger are used as A/D conversion start triggers. Figure 27.4 shows the Block Diagram of A/D Conversion Start Control Unit.
Page 471: A/D Conversion Result
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.3.4 A/D Conversion Result The A/D conversion result is stored in the ADi register (i = 0 to 7). The register where the result is stored varies depending on the A/D operating mode used.
Page 472 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter Precharge control signal Precharge External circuit example Discharge ADDDAEN control signal Analog input Chopper amp i = 8 to 11 capacitor Open Note: 1.
Page 473: One-Shot Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.4 One-Shot Mode In one-shot mode, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted once.
Page 474: Repeat Mode 0
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.5 Repeat Mode 0 In repeat mode 0, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted repeatedly.
Page 475: Repeat Mode 1
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.6 Repeat Mode 1 In repeat mode 1, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted repeatedly.
Page 476 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter “1” ADST bit in ADCON0 register “0” Successive conversion register Undefined AD0 register 1st A/D conversion result 9th A/D conversion result Undefined AD1 register 2nd A/D conversion result...
Page 477: Single Sweep Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.7 Single Sweep Mode In single sweep mode, the input voltage to two or four pins selected from among AN8 to AN11 are A/D converted once.
Page 478 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter “1” ADST bit in ADCON0 register “0” Successive conversion AN10 AN11 register Undefined AD0 register AN8 in A/D conversion result AD1 register Undefined AN9 in A/D conversion result Undefined...
Page 479: Repeat Sweep Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.8 Repeat Sweep Mode In repeat sweep mode, the input voltage to two or four pins selected from among AN8 to AN11 are A/D converted repeatedly.
Page 480 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter “1” ADST bit in ADCON0 register “0” Successive conversion AN10 AN11 AN10 AN11 register AD0 register Undefined AN8 in A/D conversion result AN8 in A/D conversion result AN8 in A/D conversion result Undefined...
Page 481: Internal Equivalent Circuit Of Analog Input
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.9 Internal Equivalent Circuit of Analog Input Figure 27.10 shows the Internal Equivalent Circuit of Analog Input. VCC VSS AVCC ON Resistor TBD k Ω...
Page 482: 27.10 Output Impedance Of Sensor Under A/D Conversion
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.10 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 27.11 has to be completed within a specified period of time.
Page 483: 27.11 Notes On A/D Converter
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 27. A/D Converter 27.11 Notes on A/D Converter • Write to the ADMOD register, the ADINSEL register, the ADCON0 register (other than ADST bit), the ADCON1 register, the OCVREFCR register when A/D conversion is stopped (before a trigger occurs).
Page 484: 28. Comparator A
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28. Comparator A Comparator A compares a reference input voltage and an analog input voltage. Comparator A1 and comparator A2 are independent of each other.
Page 485 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A Shared with voltage monitor 1 VW1F1 to VW1F0 circuit = 00b fOCO-S Sampling clock = 01b fOCO-S/2 = 10b CM1POR Pin output fOCO-S/4 selection circuit VCA26...
Page 486: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.2 Registers 28.2.1 Voltage Monitor Circuit/Comparator A Control Register (CMPA) Address 0030h Symbol COMPSEL — IRQ2SEL IRQ1SEL CM2OE CM1OE CM2POR CM1POR After Reset Symbol Bit Name...
Page 487: Voltage Detect Register (Vca1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.2.3 Voltage Detect Register (VCA1) Address 0033h Symbol — — — — VCA13 — — — After Reset Symbol Bit Name Function —...
Page 488: Voltage Detect Register 2 (Vca2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.2.4 Voltage Detect Register 2 (VCA2) Address 0034h Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. After Reset The LVDAS bit in the OFS register is set to 0.
Page 489: Voltage Monitor 1 Circuit Control Register (Vw1C)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.2.5 Voltage Monitor 1 Circuit Control Register (VW1C) Address 0039h Symbol VW1C7 — VW1F1 VW1F0 VW1C3 VW1C2 VW1C1 VW1C0 After Reset Symbol Bit Name Function...
Page 490: Voltage Monitor 2 Circuit Control Register (Vw2C)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.2.6 Voltage Monitor 2 Circuit Control Register (VW2C) Address 003Ah Symbol VW2C7 VW2C6 VW2F1 VW2F0 VW2C3 VW2C2 VW2C1 VW2C0 After Reset Symbol Bit Name Function...
Page 491: Monitoring Comparison Results
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.3 Monitoring Comparison Results 28.3.1 Monitoring Comparator A1 Once the following settings are made, the comparison result of comparator A1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 32.
Page 492: Functional Description
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.4 Functional Description Comparator A1 and comparator A2 operate independently. The comparison result of the reference input voltage and analog input voltage can be read by software. The result can also be output from the LVCOUTi (i = 1 or 2) pin.
Page 493 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A LVCMP1 Reference voltage (LVREF) VW1C3 bit Sampling clock of Sampling clock of digital filter × 2 cycles digital filter × 2 cycles VW1C2 bit Set to 0 by a program.
Page 494 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A LVCMP1 Reference voltage (LVREF) VW1C3 bit Set to 0 by a program. VW1C2 bit Set to 0 when an interrupt request is acknowledged or by a program.
Page 495: Comparator A2
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.4.2 Comparator A2 Table 28.4 lists the Procedure for Setting Bits Associated Comparator A2 Interrupt, Figure 28.4 shows a Comparator A2 Operating Example (Digital Filter Enabled), and Figure 28.5 shows a Comparator 2 Operating Example (Digital Filter Disabled).
Page 496 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A LVCMP2 Reference voltage (LVREF) VCA13 bit Sampling clock of Sampling clock of digital filter × 2 cycles digital filter × 2 cycles VW2C2 bit Set to 0 by a program.
Page 497 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A VCMP2 Reference voltage (LVREF) VCA13 bit Set to 0 by a program. VW2C2 bit Set to 0 when an interrupt request is acknowledged or by a program.
Page 498: Comparator A1 And Comparator A2 Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 28. Comparator A 28.5 Comparator A1 and Comparator A2 Interrupts Comparator A generates an interrupt request from two sources, comparator A1 and comparator A2. Non-maskable or maskable can be selected for each interrupt type.
Page 499: 29. Comparator B
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B 29. Comparator B Comparator B compares a reference input voltage and an analog input voltage. Comparator B1 and comparator B3 are independent of each other.
Page 500 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B Table 29.2 I/O Pins Pin Name Function IVCMP1 Input Comparator B1 analog pin IVREF1 Input Comparator B1 reference voltage pin IVCMP3 Input Comparator B3 analog pin IVREF3...
Page 501: Registers
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B 29.2 Registers 29.2.1 Comparator B Control Register (INTCMP) Address 01F8h Symbol INT3COUT — — INT3CP0 INT1COUT — — INT1CP0 After Reset Symbol Bit Name Function...
Page 502: Int Input Filter Select Register 0 (Intf)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B 29.2.3 INT Input Filter Select Register 0 (INTF) Address 01FCh Symbol INT3F1 INT3F0 — — INT1F1 INT1F0 INT0F1 INT0F0 After Reset Symbol Bit Name Function...
Page 503: Functional Description
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B 29.3 Functional Description Comparator B1 and comparator B3 operate independently. Their operations are the same. Table 29.3 lists the Procedure for Setting Registers Associated with Comparator B. Table 29.3 Procedure for Setting Registers Associated with Comparator B Step...
Page 504: Comparator Bi Digital Filter (I = 1 Or 3)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B 29.3.1 Comparator Bi Digital Filter (i = 1 or 3) Comparator Bi can use the same digital filter as the INTi input. The sampling clock can be selected by bits INTiF1 and INTiF0 in the INTF register.
Page 505: Comparator B1 And Comparator B3 Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 29. Comparator B 29.4 Comparator B1 and Comparator B3 Interrupts Comparator B generates an interrupt request from two sources, comparator B1 and comparator B3. The comparator Bi (i = 1 or 3) interrupt uses the same INTiIC register (bits IR and ILVL0 to ILVL2) as the INTi (i = 1 or 3) and a single vector.
Page 506: 30. Flash Memory
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30. Flash Memory The flash memory can perform in the following three rewrite modes: CPU rewrite mode, standard serial I/O mode, and parallel I/O mode.
Page 507: Memory Map
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.2 Memory Map The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 30.1 show the R8C/32A Group Flash Memory Block Diagrams. The user ROM area contains program ROM and data flash.
Page 508: Functions To Prevent Flash Memory From Being Rewritten
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.3 Functions to Prevent Flash Memory from being Rewritten Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily.
Page 509: Rom Code Protect Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.3.2 ROM Code Protect Function The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased using the OFS register in parallel I/O mode.
Page 510: Cpu Rewrite Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer.
Page 511: Flash Memory Status Register (Fst)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.1 Flash Memory Status Register (FST) Address 01B2h Symbol FST7 FST6 FST5 FST4 — LBDATA BSYAEI RDYSTI After Reset Symbol Bit Name Function RDYSTI Flash ready status interrupt request 0: No flash ready status interrupt request...
Page 512 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory BYSAEI Bit (Flash Access Error Interrupt Request Flag) The BYSAEI bit is set to 1 (flash access error interrupt request) when the BSYAEIE bit in the FMR0 register is set to 1 (flash access error interrupt enabled) and the block during auto-programming/auto-erasure is accessed.
Page 513: Flash Memory Control Register 0 (Fmr0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.2 Flash Memory Control Register 0 (FMR0) Address 01B4h Symbol RDYSTIE BSYAEIE CMDERIE CMDRST FMSTP FMR02 FMR01 — After Reset Symbol Bit Name Function —...
Page 514 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory FMSTP Bit (Flash Memory Stop Bit) This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current consumed by the flash memory.
Page 515: Flash Memory Control Register 1 (Fmr1)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.3 Flash Memory Control Register 1 (FMR1) Address 01B5h Symbol FMR17 FMR16 FMR15 FMR14 FMR13 FMR12 FMR11 FMR10 After Reset Symbol Bit Name Function FMR10 Nothing is assigned.
Page 516 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory FMR14 Bit (Data Flash Block A Rewrite Disable Bit) When the FMR 14 bit is set to 0, data flash block A accepts program and block erase commands. FMR15 Bit (Data Flash Block B Rewrite Disable Bit) When the FMR 15 bit is set to 0, data flash block B accepts program and block erase commands.
Page 517: Flash Memory Control Register 2 (Fmr2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.4 Flash Memory Control Register 2 (FMR2) Address 01B6h Symbol FMR27 — — — — FMR22 FMR21 FMR20 After Reset Symbol Bit Name Function FMR20 Erase-suspend enable bit...
Page 518: Ew0 Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.5 EW0 Mode When the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), the MCU enters CPU rewrite mode and software commands can be accepted.
Page 519: How To Set And Exit Each Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.8 How to Set and Exit Each Mode Figure 30.3 shows How to Set and Exit EW0 Mode and Figure 30.4 shows How to Set and Exit EW0 Mode (When Rewriting Data Flash) and EW1 Mode.
Page 520: Bgo (Background Operation) Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.9 BGO (BackGround Operation) Function When the program ROM area is specified while a program or block erase operation to the data flash, array data can be read.
Page 521: 30.4.10 Data Protect Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.10 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR13 bit in the FMR1 register is set to 0 (lock bit enabled).
Page 522: 30.4.11 Software Commands
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.11 Software Commands The software commands are described below. Read or write commands and data in 8-bit units. Table 30.4 Software Commands First Bus Cycle Second Bus Cycle Command...
Page 523: Program Command
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.11.4 Program Command The program command is used to write data to the flash memory in 1-byte units. When 40h is written in the first bus cycle and data is written in the second bus cycle to the write address, auto- programming (data program and verify operation) starts.
Page 524 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Flash ready status Start interrupt RDYSTIE = 1 Status check Write the command code 40h RDYSTI = 0 I = 1 (interrupt enabled) REIT Write data to the write address RDYSTI: Bit in FST register...
Page 525 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.11.5 Block Erase Command When 20h is written in the first bus cycle and then D0h is written in the second bus cycle to any block address, auto-erasure (erase and erase verify operation) starts in the specified block.
Page 526 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Start Write the command code 20h Write D0h to any block address FST7 = 1? Full status check Block erase completed FST7: Bit in FST register Figure 30.9 Block Erase Flowchart (Flash Ready Status Interrupt Disabled)
Page 527 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Start Maskable interrupt FMR20 = 1 FMR21 = 1 Write the command code 20h FST6 = 1? I = 1 (interrupt enabled) Access the flash memory Write D0h to any block address FMR21 = 0...
Page 528 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Start Maskable interrupt RDYSTIE = 1 FMR21 = 1 FMR20 = 1 REIT Write the command code 20h I = 1 (interrupt enabled) Write D0h to any block address Block erase completed Flash ready status...
Page 529 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.11.6 Lock Bit Program Command This command is used to set the lock bit of any block in the program ROM area to 0 (locked). When 77h is written in the first bus cycle and D0h is written in the second bus cycle to the starting block address, 0 is written to the lock bit of the specified block.
Page 530 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.11.7 Read Lock Bit Status Command This command is used to read the lock bit status of any address in the program ROM area. When 71h written in the first bus cycle and D0h is written in the second cycle to the starting block address, the lock bit status of the specified block is stored in the LBDATA bit in the FST register.
Page 531 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.11.8 Block Blank Check Command This command is used to confirm that all addresses in any block are blank data FFh. When 25h is written in the first bus cycle and D0h is written in the second bus cycle to any block address, blank checking starts in the specified block.
Page 532: 30.4.12 Status Register
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.12 Status Register The status register indicates the operating status of the flash memory and whether erasure or programming has completed normally or terminated in error. The status of the status register can be read by the FST register. 30.4.13 Sequence Status The clear sequence status bit indicates the operating status of the flash memory.
Page 533: 30.4.17 Full Status Check
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.4.17 Full Status Check If an error occurs, bits FST4 and FST5 in the FST register are set to 1, indicating the occurrence of an error. The execution result can be confirmed by checking these status bits (full status check).
Page 534 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Command sequence error Execute the clear status register command (Set the status flags to 0) Check if the command is properly input Full status check Re-execute the command FST4 = 1...
Page 535: Standard Serial I/O Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.5 Standard Serial I/O Mode In standard serial I/O mode, a serial programmer which supports the MCU can be used to rewrite the user ROM area while the MCU is mounted on-board.
Page 536 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Table 30.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Name Description VCC, VSS Power supply input Apply the guaranteed programming and erasure voltage to the VCC pin and 0 V to the VSS pin.
Page 537 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Table 30.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) Name Description VCC, VSS Power supply input Apply the guaranteed programming and erasure voltage to the VCC pin and 0 V to the VSS pin.
Page 538: Parallel I/O Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.6 Parallel I/O Mode Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory.
Page 539: Notes On Flash Memory
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.7 Notes on Flash Memory 30.7.1 CPU Rewrite Mode 30.7.1.1 Prohibited Instructions The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK.
Page 540 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory Table 30.10 CPU Rewrite Mode Interrupts (2) • Watchdog Timer • Undefined Instruction Erase/ • Oscillation Stop Detection • INTO Instruction Mode Write Status...
Page 541: How To Access
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 30. Flash Memory 30.7.1.3 How to Access To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1.
Page 542: 31. Reducing Power Consumption
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 31. Reducing Power Consumption 31. Reducing Power Consumption 31.1 Overview This chapter describes key points and processing methods for reducing power consumption. 31.2 Key Points and Processing Methods for Reducing Power Consumption Key points for reducing power consumption are shown below.
Page 543: Reducing Internal Power Consumption
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 31. Reducing Power Consumption 31.2.9 Reducing Internal Power Consumption When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal power consumption can be reduced by using the VCA20 bit in the VCA2 register.
Page 544: 31.2.10 Stopping Flash Memory
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 31. Reducing Power Consumption 31.2.10 Stopping Flash Memory In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by stopping the flash memory using the FMSTP bit in the FMR0 register.
Page 545: 31.2.11 Low-Current-Consumption Read Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 31. Reducing Power Consumption 31.2.11 Low-Current-Consumption Read Mode In low-speed clock mode and low-speed on-chip oscillator mode, the current consumption when reading the flash memory can be reduced by setting the FMR27 bit in the FMR2 register to 1 (enabled). Figure 31.3 shows the Handling Procedure Example of Low-Current-Consumption Read Mode.
Page 546: 32. Electrical Characteristics
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics 32. Electrical Characteristics Table 32.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit − 0.3 to 6.5 Supply voltage − 0.3 to V Input voltage P1_0 to P1_7, P3_3 to P3_5, P3_7, + 0.3...
Page 547 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.2 Recommended Operating Conditions Standard Symbol Parameter Conditions Unit Min. Typ. Max. − Supply voltage − − Supply voltage 4.0 V ≤ V ≤...
Page 548 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics 30pF Figure 32.1 Ports P1, P3, P4 Timing Measurement Circuit REJ09B0458-0010 Rev.0.10 Apr 01, 2008 Page 520 of 572...
Page 549 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.3 A/D Converter Characteristics Standard Symbol Parameter Conditions Unit Min. Typ. Max. − − − Resolution = AV − − Integral non-linearity error 10-bit mode = AV...
Page 550 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.4 Comparator A Electrical Characteristics Standard Symbol Parameter Condition Unit Min. Typ. Max. − LVREF External reference voltage input range −...
Page 551 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
Page 552 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. − 40 ° C for D version.
Page 553 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.8 Voltage Detection 0 Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min. Typ. Max. At the falling of V 1.80 1.90 2.00...
Page 554 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.10 Voltage Detection 2 Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min. Typ. Max. At the falling of V 3.80 4.00 4.20...
Page 555 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.12 High-speed On-Chip Oscillator Circuit Electrical Characteristics Standard Symbol Parameter Condition Unit Min. Typ. Max. = 25 ° C fOCO40M High-speed on-chip oscillator frequency after = 5.0 V, T reset...
Page 556 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.15 Timing Requirements of Clock Synchronous Serial I/O with Chip Select Standard Symbol Parameter Conditions Unit Min. Typ. Max. − −...
Page 557 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 or V SCS (output) or V FALL RISE SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SUCYC...
Page 558 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 or V SCS (input) or V FALL RISE LEAD SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SUCYC...
Page 559 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics or V SSCK or V SUCYC SSO (output) SSI (input) Figure 32.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) REJ09B0458-0010 Rev.0.10 Apr 01, 2008...
Page 560 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.16 Timing Requirements of I C bus Interface Standard Symbol Parameter Condition Unit Min. Typ. Max. − − SCL input cycle time + 600 −...
Page 561 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.17 Electrical Characteristics (1) [V = 5 V] Standard Symbol Parameter Condition Unit Min. Typ. Max. = − 20 mA −...
Page 562 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.18 Electrical Characteristics (2) [Vcc = 5 V] = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Standard Symbol Parameter...
Page 563 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: V = 5 V, V = 0 V at Topr = 25°C) [V = 5 V] Table 32.19 XIN Input, XCIN Input Standard...
Page 564 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.21 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLKi input cycle time c(CK) − CLKi input “H” width W(CKH) −...
Page 565 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.23 Electrical Characteristics (3) [V = 3 V] Standard Symbol Parameter Condition Unit Min. Typ. Max. = − 5 mA −...
Page 566 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.24 Electrical Characteristics (4) [Vcc = 3 V] = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Standard Symbol Parameter...
Page 567 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Timing requirements (Unless Otherwise Specified: V = 3 V, V = 0 V at Topr = 25°C) [V = 3 V] Table 32.25 XIN Input, XCIN Input Standard...
Page 568 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.27 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLKi input cycle time c(CK) − CLKi input “H” width W(CKH) −...
Page 569 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.29 Electrical Characteristics (5) [V = 2.2 V] Standard Symbol Parameter Condition Unit Min. Typ. Max. = − 2 mA −...
Page 570 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.30 Electrical Characteristics (6) [Vcc = 2.2 V] = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Standard Symbol Parameter...
Page 571 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Timing requirements (Unless Otherwise Specified: V = 2.2 V, V = 0 V at Topr = 25°C) [V = 2.2 V] Table 32.31 XIN Input, XCIN Input Standard...
Page 572 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 32. Electrical Characteristics Table 32.33 Serial Interface Standard Symbol Parameter Unit Min. Max. − CLKi input cycle time c(CK) − CLKi input “H” width W(CKH) −...
Page 573: 33. Usage Notes
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33. Usage Notes 33.1 Notes on Clock Generation Circuit 33.1.1 Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode).
Page 574: Notes On Interrupts
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.2 Notes on Interrupts 33.2.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence.
Page 575: Changing Interrupt Sources
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.2.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes.
Page 576: Rewriting Interrupt Control Register
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.2.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that register are generated.
Page 577: Notes On Id Code Areas
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.3 Notes on ID Code Areas 33.3.1 Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction.
Page 578: Notes On Dtc
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.5 Notes on DTC 33.5.1 DTC activation source • Do not generate any DTC activation sources before entering wait mode or during wait mode. •...
Page 579: Notes On Timer Ra
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.6 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts.
Page 580: Notes On Timer Rb
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.7 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts.
Page 581: Programmable Wait One-Shot Generation Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.7.4 Programmable Wait One-shot Generation Mode To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to 1), note the following points: •...
Page 582: Notes On Timer Rc
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.8 Notes on Timer RC 33.8.1 TRC Register • The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at compare match with TRCGRA register).
Page 583: Input Capture Function
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes • After switching the count source from fOCO-F to fOCO40M, allow a minimum of two cycles of fOCO-F to elapse after changing the clock setting before stopping fOCO-F. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops).
Page 584: Notes On Timer Re
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.9 Notes on Timer RE 33.9.1 Starting and Stopping Count Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop.
Page 585 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes TSTART in TRECR1 = 0 Stop timer RE operation TCSTF in TRECR1 = 0? TREIC ← 00h (disable timer RE interrupt) TRERST in TRECR1 = 1 Timer RE register and control circuit reset...
Page 586: Time Reading Procedure Of Real-Time Clock Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.9.3 Time Reading Procedure of Real-Time Clock Mode In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Page 587: Notes On Serial Interface (Uart0)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.10 Notes on Serial Interface (UART0) • When reading data from the U0RB register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units.
Page 588: Notes On Serial Interface (Uart2)
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.11 Notes on Serial Interface (UART2) 33.11.1 Clock Synchronous Serial I/O Mode 33.11.1.1 Transmission/Reception When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is ready for a receive operation.
Page 589: 33.11.2 Clock Asynchronous Serial I/O (Uart) Mode
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.11.2 Clock Asynchronous Serial I/O (UART) Mode 33.11.2.1 Transmission/Reception When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the transmitting side that the MCU is ready for a receive operation.
Page 590: 33.12 Notes On Synchronous Serial Communication Unit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.12 Notes on Synchronous Serial Communication Unit Set the IICSEL bit in the SSUIICSR register to 0 (select SSU function) to use the synchronous serial communication unit function.
Page 591: Usage Notes
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.16 Notes on Flash Memory 33.16.1 CPU Rewrite Mode 33.16.1.1 Prohibited Instructions The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK.
Page 592 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes Table 33.2 CPU Rewrite Mode Interrupts (2) • Watchdog Timer • Undefined Instruction Erase/ • Oscillation Stop Detection • INTO Instruction Mode Write Status...
Page 593 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.16.1.3 How to Access To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1.
Page 594: 33.17 Notes On Noise
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 33. Usage Notes 33.17 Notes on Noise 33.17.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
Page 595: Notes On On-Chip Debugger
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 34. Notes on On-Chip Debugger 34. Notes on On-Chip Debugger When using the on-chip debugger to develop and debug programs for the R8C/32A Group, take note of the following: (1) Some of the user flash memory and RAM areas are used by the on-ship debugger.
Page 596: Appendix 1. Package Dimensions
Specifications in this manual are tentative and subject to change. R8C/32A Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LSSOP20-4.4x6.5-0.65...
Page 597: Appendix 2. Connection Examples Between Serial Writer And On-Chip Debugging Emulator
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows a Connection Example with E8a Emulator (R0E00008AKCE00).
Page 598: Appendix 3. Example Of Oscillation Evaluation Circuit
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Appendix 3. Example of Oscillation Evaluation Circuit Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit. RESET Connect oscillation...
Page 599 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Index Index [ A ] [ L ] ADCON0 ................438 LINCR .................. 420 ADCON1 ................439 LINCR2 ................419 ADi (i = 0 to 7) ..............435 LINST ..................
Page 600 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Index TRBSC ................204 [ W ] TRC ..................228 WDTC .................. 159 TRCADCR ................230 WDTR .................. 158 TRCCR1 ............225, 246, 254, 260 WDTS ..................
Page 601: Revision History Revision History
REVISION HISTORY R8C/32A Group Hardware Manual R8C/32A Group Hardware Manual REVISION HISTORY Description Rev. Date Page Summary − 0.10 Apr 01, 2008 First Edition issued C - 1...
Page 602 R8C/32A Group Hardware Manual Publication Date: Rev.0.10 Apr 01, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan...
Page 603 R8C/32A Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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