R8C/18 Group, R8C/19 Group
Timer Z Output Control Register
b7 b6 b5 b4
b3 b2 b1 b0
0
NOTES:
1.
This bit is set to 0 w hen the output of one-shot w aveform is completed. If the TZS bit in the TZMR register w as set to
0 (count stops) to stop the w aveform output during one-shot w aveform output, set the TZOS bit to 0.
2.
This bit is enabled only w hen operating in programmable w aveform generation mode.
3.
When executing an instruction w hich changes this register w hen the TZOS bit is set to 1 (during count), the TZOS
bit is automatically set to 0 (one-shot stop) if the count is completed w hile the instruction is being executed. If this
causes problems, execute an instruction w hich changes the contents of this register w hen the TZOS bit is set to 0
(one-shot stop).
Timer Z Waveform Output Control Register
b7 b6 b5 b4
b3 b2
b1 b0
0
0
0
0
0
NOTES:
1.
The INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to 0 (one edge).
2.
Set the INOSTG bit to 1 after setting the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register.
Figure 14.14
Registers TZOC and PUM
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
(3)
Symbol
Address
008Ah
TZOC
Bit Symbol
Bit Name
Timer Z one-shot start bit
TZOS
—
Reserved bit
(b1)
Timer Z programmable w aveform
TZOCNT
generation output sw itch bit
—
Nothing is assigned. If necessary, set to 0.
(b7-b3)
When read, the content is 0.
Symbol
Address
0084h
PUM
Bit Symbol
Bit Name
Reserved bits
—
(b4-b0)
Timer Z output level latch
TZOPL
_____
INT0
pin one-shot trigger control
INOSTG
(2)
bit (timer Z)
_____
INT0
pin one-shot trigger polarity
INOSEG
select bit (timer Z)
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(1)
0 : One-shot stops.
1 : One-shot starts.
Set to 0.
0 : Outputs programmable w aveform.
(2)
1 : Outputs value in P1_3 port register.
Set to 0.
Function varies depending on operating
mode.
_____
0 : INT0
pin one-shot trigger disabled
_____
1 : INT0
pin one-shot trigger enabled
0 : Falling edge trigger
1 : Rising edge trigger
(1)
14. Timers
After Reset
00h
Function
After Reset
00h
Function
RW
RW
RW
RW
—
RW
RW
RW
RW
RW