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R8C/18 Group, R8C/19 Group
17.4
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the
CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board
without using a ROM programmer. Execute the program and block erase commands only to blocks in the
user ROM area.
The flash module has an erase-suspend function when an interrupt request is generated during an erase
operation in CPU rewrite mode. It performs an interrupt process after the erase operation is halted
temporarily. During erase-suspend, the user ROM area can be read by a program.
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the
flash module has a program-suspend function which performs the interrupt process after the
auto-program operation. During program-suspend, the user ROM area can be read by a program.
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode).
Table 17.3 lists the Differences between EW0 Mode and EW1 Mode.
Table 17.3
Differences between EW0 Mode and EW1 Mode
Item
Operating mode
Areas in which a rewrite
control program can be
located
Areas in which a rewrite
control program can be
executed
Areas which can be
rewritten
Software command
restrictions
Modes after program or
erase
CPU status during auto-
write and auto-erase
Flash memory status
detection
Conditions for transition to
erase-suspend
Conditions for transitions to
program-suspend
CPU clock
NOTE:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting
the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enabled).
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
EW0 Mode
Single-chip mode
User ROM area
Necessary to transfer to any area other
than the flash memory (e.g., RAM) before
executing.
User ROM area
None
Read status register mode
Operating
• Read bits FMR00, FMR06, and FMR07
in the FMR0 register by a program.
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Set bits FMR40 and FMR41 in the FMR4
register to 1 by a program.
Set bits FMR40 and FMR42 in the FMR4
register to 1 by a program.
5 MHz or below
Page 178 of 233
17. Flash Memory Version
EW1 Mode
Single-chip mode
User ROM area
Executing directly in user ROM area is
possible.
User ROM area
However, blocks which contain a rewrite
control program are excluded.
• Program and block erase commands
• Cannot be run on any block which
contains a rewrite control program
• Read status register command cannot be
executed
Read array mode
Hold state (I/O ports hold state before the
command is executed)
Read bits FMR00, FMR06, and FMR07 in
the FMR0 register by a program.
The FMR40 bit in the FMR4 register is set
to 1 and the interrupt request of the
enabled maskable interrupt is generated.
The FMR40 bit in the FMR4 register is set
to 1 and the interrupt request of the
enabled maskable interrupt is generated.
No restriction (on clock frequency to be
used)
(1)
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