Renesas R8C/18 Series Hardware Manual page 123

R8C/18 Group, R8C/19 Group
Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 1
NOTES:
1. The IR bit in the INT1IC register may be set to 1 (requests interrupt) w hen the R0EDG bit is rew ritten.
Refer to 12.5.5 Changing Interrupt Sources.
2. Refer to 14.1.6 Notes on Tim er X for precautions regarding the TXS bit.
Figure 14.5 TXMR Register in Pulse Output Mode
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
008Bh
TXMR
Bit Symbol Bit Name
Operating mode select bits 0, 1
TXMOD0
TXMOD1
_____
INT1 /CNTR0 signal
R0EDG
polarity sw itch bit
Timer X count start flag
TXS
________
P3_7/CNTR0 select bit
TXOCNT
TXMOD2 Set to 0 in pulse output mode.
TXEDG Set to 0 in pulse output mode.
TXUND Set to 0 in pulse output mode.
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b1 b0
0 1 : Pulse output mode
0 : CNTR0 signal output starts at "H".
1 : CNTR0 signal output starts at "L".
(1)
(2)
0 : Stops counting.
1 : Starts counting.
0 : Port P3_7
________
1 : CNTR0 output
After Reset
00h
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW