Renesas R8C/18 Series Hardware Manual page 165

R8C/18 Group, R8C/19 Group
UARTi Transmit/Receive Control Register 0 (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTE:
1. If the BRG count source is sw itched, set the UiBRG register again.
Figure 15.5 Registers U0C0 to U1C0
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
00A4h
U0C0
00ACh
U1C0
Bit Symbol Bit Name
BRG count source select
(1)
bits
CLK0
CLK1
—
Reserved bit
(b2)
Transmit register empty
flag
TXEPT
— Nothing is assigned. If necessary, set to 0.
(b4) When read, the content is 0.
Data output select bit
NCH
CLK polarity select bit
CKPOL
Transfer format select bit 0 : LSB first
UFORM
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After Reset
08h
08h
Function
b1 b0
0 0 : Selects f1.
0 1 : Selects f8.
1 0 : Selects f32.
1 1 : Do not set.
Set to 0.
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
0 : TXDi pin is for CMOS output.
1 : TXDi pin is for N-channel open drain output.
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge.
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge.
1 : MSB first
15. Serial Interface
RW
RW
RW
RW
RO
—
RW
RW
RW