Renesas R8C/18 Series Hardware Manual page 93

R8C/18 Group, R8C/19 Group
INT0 Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES:
1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.5.6 Changing Interrupt Control Register Contents.
3. If the INTOPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.5.5 Changing Interrupt
Sources.
Figure 12.4 INT0IC Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
(2)
Symbol Address
005Dh
INT01C
Bit Symbol Bit Name
Interrupt priority level select bits
ILVL0
ILVL1
ILVL2
Interrupt request bit
IR
Polarity sw itch bit
POL
— Reserved bit
(b5)
— Nothing is assigned. If necessary, set to 0.
(b7-b6) When read, the content is undefined.
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b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt.
1 : Requests interrupt.
(4)
0 : Selects falling edge.
1 : Selects rising edge.
Set to 0.
12. Interrupts
After Reset
XX00X000b
Function
RW
(3)
RW
RW
RW
RW
(1)
RW
RW
—