Renesas R8C/18 Series Hardware Manual page 138

R8C/18 Group, R8C/19 Group
Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
NOTES:
1. When the TZS bit is set to 1 (count starts), the setting value in the TZWC bit is enabled. When the TZWC bit is set to
0, timer Z count value is w ritten to both reload register and counter. Timer Z count value is w ritten to the reload
register only w hen the TZWC bit is set to 1. When the TZS bit is set to 0 (count stops), timer Z count value is w ritten
to both reload register and counter regardless of the setting value of the TZWC bit.
2. Refer to 14.2.5 Notes on Tim er Z for precautions regarding the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0
Figure 14.16 Registers TZMR and PUM in Timer Mode
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
0080h
TZMR
Bit Symbol Bit Name
— Reserved bits
(b3-b0)
TZMOD0 Timer Z operating mode
bits
TZMOD1
Timer Z w rite control bit
TZWC
Timer Z count start flag
TZS
Symbol Address
0084h
PUM
Bit Symbol Bit Name
— Reserved bits
(b4-b0)
Timer Z output level latch
TZOPL
_____
INT0 pin one-shot trigger
INOSTG
control bit
_____
INT0 pin one-shot trigger
INOSEG
polarity select bit
Page 123 of 233
After Reset
Function
Set to 0.
b5 b4
0 0 : Timer mode
(1)
0 : Write to reload register and counter
1 : Write to reload register only
(2)
0 : Stops counting.
1 : Starts counting.
After Reset
Function
Set to 0.
Set to 0 in timer mode.
Set to 0 in timer mode.
Set to 0 in timer mode.
14. Timers
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW