Renesas R8C/18 Series Hardware Manual page 140

R8C/18 Group, R8C/19 Group
Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 0
NOTES:
1. When the TZS bit is set to 1 (count starts), the count value is w ritten to the reload register only. When the TZS bit is
set to 0 (count stops), the count value is w ritten to both reload register and counter.
2. Refer to 14.2.5 Notes on Tim er Z for precautions regarding the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Figure 14.17 Registers TZMR and PUM in Programmable Waveform Generation Mode
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
0080h
TZMR
Bit Symbol Bit Name
— Reserved bits
(b3-b0)
TZMOD0 Timer Z operating mode bits
TZMOD1
Timer Z w rite control bit
TZWC
Timer Z count start flag
TZS
Symbol Address
0084h
PUM
Bit Symbol Bit Name
— Reserved bits
(b4-b0)
Timer Z output level latch
TZOPL
_____
INT0 pin one-shot trigger
INOSTG
control bit
_____
INT0 pin one-shot trigger
INOSEG
polarity select bit
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After Reset
Function
Set to 0.
b5 b4
0 1 : Programmable w aveform generation mode
Set to 1 in programmable w aveform generation
(1)
mode.
(2)
0 : Stops counting.
1 : Starts counting.
After Reset
Function
Set to 0.
0 : Outputs "H" for primary period.
Outputs "L" for secondary period.
Outputs "L" w hen the timer is stopped.
1 : Outputs "L" for primary period.
Outputs "H" for secondary period.
Outputs "H" w hen the timer is stopped.
Set to 0 in programmable w aveform generation
mode.
Set to 0 in programmable w aveform generation
mode.
14. Timers
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW