Renesas R8C/18 Series Hardware Manual page 147

R8C/18 Group, R8C/19 Group
Timer Z Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 0 0 0 0
NOTES:
1. When the TZS bit is set to 1 (count starts), the count value is w ritten to the reload register only. When the TZS bit is
set to 0 (count stops), the count value is w ritten to both reload register and counter.
2. Refer to 14.2.5 Notes on Tim er Z for precautions regarding the TZS bit.
Timer Z Waveform Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
NOTES:
1. Set the INOSTG bit to 1 after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register
are set. When setting the INOSTG bit to 1 (INT0
in the INT0F register. Set the INOSTG bit to 0 (INT0
TZMR register is set to 0 (count stops).
2. The INOSEG bit is enabled only w hen the INT0PL bit in the INTEN register is set to 0 (one edge).
Figure 14.21 Registers TZMR and PUM in Programmable Wait One-Shot Generation Mode
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
0080h
TZMR
Bit Symbol Bit Name
— Reserved bits
(b3-b0)
Timer Z operating mode
TZMOD0
bits
TZMOD1
Timer Z w rite control bit
TZWC
Timer Z count start flag
TZS
Symbol Address
0084h
PUM
Bit Symbol Bit Name
— Reserved bits
(b4-b0)
Timer Z output level latch
TZOPL
_____
INT0 pin one-shot trigger
INOSTG
(1)
control bit
_____
INT0 pin one-shot trigger
INOSEG
polarity select bit
_____
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Set to 0.
b5 b4
1 1 : Programmable w ait one-shot generation mode
Set to 1 in programmable w ait one-shot generation
(1)
mode.
(2)
0 : Stops counting.
1 : Starts counting.
Set to 0.
0 : Outputs one-shot pulse "H".
Outputs "L" w hen the timer is stopped.
1 : Outputs one-shot pulse "L".
Outputs "H" w hen the timer is stopped.
_____
0 : INT0 pin one-shot trigger disabled
_____
1 : INT0 pin one-shot trigger enabled
0 : Falling edge trigger
1 : Rising edge trigger
(2)
pin one-shot trigger enabled), set bits INT0F0 to INT0F1
_____
pin one-shot trigger disabled) after the TZS bit in the
After Reset
00h
Function
After Reset
00h
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW