Renesas R8C/18 Series Hardware Manual page 70

R8C/18 Group, R8C/19 Group
System Clock Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1 0 0
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
2. The CM05 bit stops the main clock w hen the on-chip oscillator mode is selected.
Do not use this bit to detect w hether the main clock is stopped. To stop the main clock, set the bits in the follow ing
order:
(a) Set bits OCD1 and OCD0 in the OCD register to 00b (oscillation stop detection function disabled).
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
3. To input an external clock, set the CM05 bit to 1 (main clock stops) and the CM13 bit in the CM1 register to 1
(XIN-XOUT pin).
4. When the CM05 bit is set to 1 (main clock stops), P4_6 and P4_7 can be used as input ports.
5. When entering stop mode from high or medium speed mode, the CM06 bit is set to 1 (divide-by-8 mode).
Figure 10.2 CM0 Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
(1)
Symbol Address
0006h
CM0
Bit Symbol Bit Name
— Reserved bits
(b1-b0)
WAIT peripheral function clock stop
bit
CM02
— Reserved bit
(b3)
— Reserved bit
(b4)
Main clock (XIN-XOUT) stop bit
CM05
System clock division select bit 0
CM06
— Reserved bit
(b7)
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After Reset
68h
Function
Set to 0.
0 : Peripheral function clock does not stop
in w ait mode.
1 : Peripheral function clock stops in
w ait mode.
Set to 1.
Set to 0.
(2, 4)
0 : Main clock oscillates.
1 : Main clock stops. (3)
(5)
0 : CM16, CM17 enabled
1 : Divide-by-8 mode
Set to 0.
10. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW