Renesas R8C/18 Series Hardware Manual page 114

R8C/18 Group, R8C/19 Group
Watchdog Timer Reset Register
b7 b0
NOTES:
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled), 0FFFh is set in the
w atchdog timer.
Watchdog Timer Start Register
b7 b0
Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
NOTES:
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
Figure 13.3 Registers WDTR, WDTS, and CSPR
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
000Dh
WDTR
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.
The default value of the w atchdog timer is 7FFFh w hen count source protection mode is
disabled and 0FFFh w hen count source protection mode is enabled.
Symbol Address
000Eh
WDTS
The w atchdog timer starts counting after a w rite instruction to this register.
Symbol Address
001Ch
CSPR
Bit Symbol Bit Name
— Reserved bits
(b6-b0)
Count source protection mode
CSPRO
(2)
select bit
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After Reset
Undefined
Function
(1)
(2)
After Reset
Undefined
Function
After Reset
00h
Function
Set to 0.
0 : Count source protection mode disabled
1 : Count source protection mode enabled
13. Watchdog Timer
RW
WO
RW
WO
(1)
RW
RW
RW