Table of Contents
Advertisement
R8C/18 Group, R8C/19 Group
12.1.6.4
Interrupt Sequence
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt
routine execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines
its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence
from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an
interrupt request is generated while the instruction is being executed, the MCU suspends the
instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below.
Figure 12.5 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading
address 00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).
(2) The FLG register is saved to a temporary register
the interrupt sequence.
(3) The I, D, and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt numbers
32 to 63 is executed.
(4) The CPU's internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the
interrupt routine.
NOTE:
1. This register cannot be used by user.
1
2
CPU clock
Address
Address bus
0000h
Data bus
RD
WR
The undefined state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
Figure 12.5
Time Required for Executing Interrupt Sequence
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
3
4
5
6
7
Undefined
Interrupt
Undefined
information
Undefined
Page 80 of 233
(1)
in the CPU immediately before entering
(1)
is saved to the stack.
8
9
10
11
12
13
SP-2 SP-1
SP-4
SP-3
SP-3
SP-2
SP-1
SP-4
contents
contents
contents
contents
12. Interrupts
14
15
16
17
18
VEC
VEC+1
VEC+2
VEC+1
VEC+2
VEC
contents
contents
contents
19
20
PC
Advertisement
Table of Contents
