Renesas R8C/18 Series Hardware Manual page 96

R8C/18 Group, R8C/19 Group
12.1.6.5 Interrupt Response Time
Figure 12.6 shows the Interrupt Response Time. The interrupt response time is the period between
an interrupt request generation and the execution of the first instruction in the interrupt routine. The
interrupt response time includes the period between interrupt request generation and the completion
of execution of the instruction (refer to (a) in Figure 12.6) and the period required to perform the
interrupt sequence (20 cycles, refer to (b) in Figure 12.6).
Interrupt request is generated. Interrupt request is acknowledged.
Figure 12.6 Interrupt Response Time
12.1.6.6 IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5
is set in the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged
Watchdog timer, oscillation stop detection, voltage monitor 2
Software, address match, single-step, address break
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Instruction Interrupt sequence
(a)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a
register is set as the divisor).
(b) 21 cycles for address match and single-step interrupts.
Interrupt Source
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Instruction in
interrupt routine
20 cycles (b)
12. Interrupts
Time
Value Set in IPL
7
Not changed