Renesas R8C/18 Series Hardware Manual page 174

R8C/18 Group, R8C/19 Group
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
Transfer clock
TE bit in UiC1
1
register
0
TI bit in UiC1 1
register
0
Start bit
TXDi
1
TXEPT bit in
UiC0 register
0
IR bit in SiTIC
1
register
0
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UCON register = 1 (an interrupt request is generated when transmit completes)
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
Transfer clock
TE bit in UiC1
1
register
0
1
TI bit in UiC1
register
0
Start bit
TXDi
TXEPT bit in 1
UiC0 register
0
IR bit in SiRIC 1
register
0
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UCON register = 0 (an interrupt request is generated when transmit buffer is empty)
Figure 15.10 Transmit Timing in UART Mode
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
TC
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
ST D0 D1 D2 D3 D4 D5 D6
TC
Write data to UiTB register
ST D0 D1 D2 D3 D4 D5 D6
Set to 0 when interrupt request is acknowledged, or set by a program
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Parity Stop
bit bit
D7 P ST D0 D1 D2 D3
SP
Set to 0 when interrupt request is acknowledged, or set by a program
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Value set in UiBRG register
I = 0 or 1
Transfer from UiTB register to UARTi transmit register
Stop Stop
bit bit
D7 D8 ST D0 D1 D2
SP SP
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Value set in UiBRG register
i = 0 or 1
15. Serial Interface
Stop pulsing
because the TE bit is set to 0
D4 D5 D6 D7 P SP
D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
ST D0 D1