Renesas R8C/18 Series Hardware Manual page 35

R8C/18 Group, R8C/19 Group
Table 4.3 SFR Information (3)
Address
0080h Timer Z Mode Register
0081h
0082h
0083h
0084h Timer Z Waveform Output Control Register
0085h Prescaler Z Register
0086h Timer Z Secondary Register
0087h Timer Z Primary Register
0088h
0089h
008Ah Timer Z Output Control Register
008Bh Timer X Mode Register
008Ch Prescaler X Register
008Dh Timer X Register
008Eh Timer Count Source Setting Register
008Fh
0090h Timer C Register
0091h
0092h
0093h
0094h
0095h
0096h External Input Enable Register
0097h
0098h Key Input Enable Register
0099h
009Ah Timer C Control Register 0
009Bh Timer C Control Register 1
009Ch Capture, Compare 0 Register
009Dh
009Eh Compare 1 Register
009Fh
00A0h UART0 Transmit/Receive Mode Register
00A1h UART0 Bit Rate Register
00A2h UART0 Transmit Buffer Register
00A3h
00A4h UART0 Transmit/Receive Control Register 0
00A5h UART0 Transmit/Receive Control Register 1
00A6h UART0 Receive Buffer Register
00A7h
00A8h UART1 Transmit/Receive Mode Register
00A9h UART1 Bit Rate Register
00AAh UART1 Transmit Buffer Register
00ABh
00ACh UART1 Transmit/Receive Control Register 0
00ADh UART1 Transmit/Receive Control Register 1
00AEh UART1 Receive Buffer Register
00AFh
00B0h UART Transmit/Receive Control Register 2
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. When the output compare mode is selected (the TCC13 bit in the TCC1 register = 1), the value is set to FFFF
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
(1)
Register
Page 20 of 233
4. Special Function Registers (SFRs)
Symbol After reset
TZMR 00h
PUM 00h
PREZ FFh
TZSC FFh
TZPR FFh
TZOC 00h
TXMR 00h
PREX FFh
TX FFh
TCSS 00h
TC 00h
00h
INTEN 00h
KIEN 00h
TCC0 00h
TCC1 00h
TM0 00h
(2)
00h
TM1 FFh
FFh
U0MR 00h
U0BRG XXh
U0TB XXh
XXh
U0C0 00001000b
U0C1 00000010b
U0RB XXh
XXh
U1MR 00h
U1BRG XXh
U1TB XXh
XXh
U1C0 00001000b
U1C1 00000010b
U1RB XXh
XXh
UCON 00h
16
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