Renesas R8C/18 Series Hardware Manual page 198

R8C/18 Group, R8C/19 Group
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 0
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
2. This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
Figure 17.6 FMR1 Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
01B5h
FMR1
Bit Symbol Bit Name
— Reserved bit
(b0)
EW1 mode select bit
FMR11
— Reserved bits
(b4-b2)
Block 0 rew rite disable bit
FMR15
Block 1rew rite disable bit
FMR16
— Reserved bit
(b7)
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When read, the content is undefined.
(1, 2)
0 : EW0 mode
1 : EW1 mode
Set to 0.
(2, 3)
0 : Enables rew rite.
1 : Disables rew rite.
(2, 3)
0 : Enables rew rite.
1 : Disables rew rite.
Set to 1.
17. Flash Memory Version
After Reset
1000000Xb
Function RW
RO
RW
RW
RW
RW
RW