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R8C/18 Group, R8C/19 Group
13.2
Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source
protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be
supplied to the watchdog timer. Table 13.3 lists the Watchdog Timer Specifications (with Count Source
Protection Mode Enabled).
Table 13.3
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item
Count source
Count operation
Period
Count start conditions
Reset condition of watchdog
timer
Count stop condition
Operation at time of
underflow
Registers, bits
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address
0FFFFh with a flash programmer.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed on-chip
oscillator clock frequency is 125 kHz
(1)
The WDTON bit
the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset).
The watchdog timer and prescaler stop after a reset and the count starts
when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after reset).
The watchdog timer and prescaler start counting automatically after a
reset.
• Reset
• Write 00h to the WDTR register before writing FFh.
• Underflow
None (The count does not stop in wait mode after the count starts. The
MCU does not enter stop mode.)
Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.)
• When setting the CSPPRO bit in the CSPR register to 1 (count source
protection mode is enabled)
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip oscillator
on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is reset
when watchdog timer underflows.)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled. (It remains
unchanged even if it is set to 1. The MCU does not enter stop mode.)
- Writing to the CM14 bit in the CM1 register is disabled. (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator does
not stop.)
Page 101 of 233
Specification
in the OFS register (0FFFFh) selects the operation of
(2)
, the following are set automatically
13. Watchdog Timer
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