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R8C/18 Group, R8C/19 Group
System Clock Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
NOTES:
1.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
2.
When entering stop mode from high or medium speed mode, this bit is set to 1 (drive capacity high).
3.
When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
4.
If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
5.
When the OCD2 bit is set to 0 (main clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped).
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip
oscillator on). And remains unchanged even if 1 is w ritten to it.
6.
When using the voltage detection interrupt, set the CM14 bit to 0 (low -speed on-chip oscillator on).
7.
When the CM10 bit is set to 1 (stop mode), or the CM05 bit in the CM0 register to 1 (main clock stops) and the CM13
bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin becomes "H".
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.
8.
In count source protect mode (refer to 13.2 Count Source Protection Mode Enabled), the value remains
unchanged even if bits CM10 and CM14 are set.
Figure 10.3
CM1 Register
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
(1)
Symbol
Address
0007h
CM1
Bit Symbol
Bit Name
All clock stop control bit
CM10
—
Reserved bit
(b1)
—
Reserved bit
(b2)
Port XIN-XOUT sw itch bit
CM13
Low -speed on-chip oscillation stop
CM14
(5, 6, 8)
bit
XIN-XOUT drive capacity select bit
CM15
System clock division select bits 1
CM16
CM17
Page 56 of 233
(4, 7, 8)
0 : Clock operates.
1 : Stops all clocks (stop mode).
Set to 0.
Set to 0.
(7)
0 : Input port P4_6, P4_7
1 : XIN-XOUT Pin
0 : Low -speed on-chip oscillator on
1 : Low -speed on-chip oscillator off
(2)
0 : Low
1 : High
(3)
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
10. Clock Generation Circuit
After Reset
20h
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
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