Renesas R8C/18 Series Hardware Manual page 129

R8C/18 Group, R8C/19 Group
Timer X Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 0
NOTES:
1. The IR bit in the INT1IC register may be set to 1 (requests interrupt) w hen the R0EDG bit is rew ritten.
Refer to 12.5.5 Changing Interrupt Sources.
2. This bit is set to 0 by w riting 0 in a program (and remains unchanged even if 1 is w ritten to it).
3. Refer to 14.1.6 Notes on Tim er X for precautions regarding the TXS bit.
Figure 14.9 TXMR Register in Pulse Period Measurement Mode
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Symbol Address
008Bh
TXMR
Bit Symbol Bit Name
Operating mode select bits 0, 1
TXMOD0
TXMOD1
_____
INT1 /CNTR0 signal
polarity sw itch bit
R0EDG
Timer X count start flag
TXS
TXOCNT Set to 0 in pulse w idth measurement mode.
TXMOD2 Operating mode select bit 2
Active edge judgment flag
(2)
TXEDG
Timer X underflow flag
(2)
TXUND
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b1 b0
0 0 : Timer mode or pulse period measurement
mode
[CNTR0]
0 : Measures measured pulse from one
(1)
rising edge to next rising edge.
1 : Measures measured pulse from one
falling edge to next falling edge.
_____
[INT1]
0 : Rising edge
1 : Falling edge
(3)
0 : Stops counting.
1 : Starts counting.
1 : Pulse period measurement mode
0 : Active edge not received
1 : Active edge received
0 : No underflow
1 : Underflow
After Reset
00h
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW