Renesas R8C/18 Series Hardware Manual page 72

R8C/18 Group, R8C/19 Group
Oscillation Stop Detection Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to this register.
2. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a main clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b (oscillation stop detection function enabled). If the OCD3 bit is set to 1 (main
clock stops), the OCD2 bit remains unchanged even w hen set to 0 (main clock selected).
3. The OCD3 bit is enabled w hen bits OCD1 to OCD0 are set to 11b (oscillation stop detection function enabled).
4. Set bits OCD1 to OCD0 to 00b (oscillation stop detection function disabled) before entering stop or on-chip oscillator
mode (main clock stops).
5. The OCD3 bit remains 0 (main clock oscillates) if bits OCD1 to OCD0 are set to 00b.
6. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
7. Refer to Figure 10.9 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to Main
Clock for the sw itching procedure w hen the main clock re-oscillates after detecting an oscillation stop.
Figure 10.4 OCD Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
(1)
Symbol Address
000Ch
OCD
Bit Symbol Bit Name
Oscillation stop detection enable
bits
OCD0
OCD1
System clock select bit
OCD2
(3, 5)
Clock monitor bit
OCD3
— Reserved bits
(b7-b4)
Page 57 of 233
After Reset
b1 b0
0 0 : Oscillation stop detection function
disabled
0 1 : Do not set.
1 0 : Do not set.
1 1 : Oscillation stop detection function
(4, 7)
enabled
(6)
0 : Selects main clock.
1 : Selects on-chip oscillator clock.
0 : Main clock oscillates.
1 : Main clock stops.
Set to 0.
10. Clock Generation Circuit
04h
Function
(7)
(2)
RW
RW
RW
RW
RO
RW